While this is not a wonderful organizing principle, it
does make it easy to find routines, and clear where to
insert new ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53672 91177308-0d34-0410-b5e6-96231b3b80d8
In LegalizeDAG the value is zero-extended to
the new type before byte swapping. It doesn't
matter how the extension is done since the new
bits are shifted off anyway after the swap, so
extend by any old rubbish bits. This results
in the final assembler for the testcase being
one line shorter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53604 91177308-0d34-0410-b5e6-96231b3b80d8
than the vector element type. Don't forget to
handle this when the insertion index is not a
constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53556 91177308-0d34-0410-b5e6-96231b3b80d8
extending load of a vector. Handle this case when
splitting vector loads. I'm not completely sure
what is supposed to happen, but I think it means
hi should be set to undef. LegalizeDAG does not
consider this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53555 91177308-0d34-0410-b5e6-96231b3b80d8
stores of one-element vectors. Also, neaten the
handling of INSERT_VECTOR_ELT when the inserted
type is larger than the vector element type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53554 91177308-0d34-0410-b5e6-96231b3b80d8
are used for passing huge immediates in inline ASM
from the front-end straight down to the ASM writer.
Of course this is a hack, but it is simple, limited
in scope, works in practice, and is what LegalizeDAG
does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53553 91177308-0d34-0410-b5e6-96231b3b80d8
8 %reg1024<def> = IMPLICIT_DEF
12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
The live range [12, 14) are not part of the r1024 live interval since it's defined by an implicit def. It will not conflicts with live interval of r1025. Now suppose both registers are spilled, you can easily see a situation where both registers are reloaded before the INSERT_SUBREG and both target registers that would overlap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53503 91177308-0d34-0410-b5e6-96231b3b80d8
use a timer group for the timers in SelectionDAGISel. Also,
Split scheduling out from emitting, to give each their own
timer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53476 91177308-0d34-0410-b5e6-96231b3b80d8
SINT_TO_FP libcall plus additional operations:
it might as well be a direct UINT_TO_FP libcall.
So only turn it into an SINT_TO_FP if the target
has special handling for SINT_TO_FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53461 91177308-0d34-0410-b5e6-96231b3b80d8
when working on legalizetypes. Both legalizetypes and legalizeops now
produce hte same code for CodeGen/ARM/fcopysign.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53435 91177308-0d34-0410-b5e6-96231b3b80d8
Lack of these caused a bootstrap failure with Fortran
on x86-64 with LegalizeTypes turned on. While there,
be nice to 16 bit machines and support expansion of
i32 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53408 91177308-0d34-0410-b5e6-96231b3b80d8
- Change local register allocator to use the new isRegReDefinedByTwoAddr instead of reinventing the wheel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53394 91177308-0d34-0410-b5e6-96231b3b80d8
makes their special-case checks of use_size() less beneficial,
so remove them. This eliminates all but one use of use_size(),
which is in AssignTopologicalOrder, which uses it only once for
each node, and so can reasonably afford to recompute it, as
this allows the UsesSize field of SDNode to be removed
altogether.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53377 91177308-0d34-0410-b5e6-96231b3b80d8
