Commit Graph

10658 Commits

Author SHA1 Message Date
Bob Wilson
973a074345 Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
Auto-upgrade the old intrinsic and update tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 20:02:30 +00:00
Chris Lattner
1875ce4ad9 two changes:
1) nuke ConstDataCoalSection, which is dead.
2) revise my previous patch for rdar://8018335,
  which was completely wrong.  Specifically, it doesn't 
  make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS,
  because it is for readonly data.  templates (it turns out)
  go to const_coal_nt.  The real fix for rdar://8018335 was
  to give ConstTextCoalSection a section kind of ReadOnly 
  instead of Text.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 18:12:35 +00:00
Michael J. Spencer
7b8167484c Partially revert r112480. Caused test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112486 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 15:34:08 +00:00
NAKAMURA Takumi
8794dd794e coff-dump.py: Fix PR7996. Now it is compatible to Python-2.4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 15:19:56 +00:00
Michael J. Spencer
17d3983730 Fix constant-over-index.ll test on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112483 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 15:08:02 +00:00
Michael J. Spencer
06b7f58522 Test: Fix LLVMC tests on CMake.
The CMake build didn't define TEST_COMPILE_CXX_CMD. The tests assumed gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112480 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 14:49:00 +00:00
Duncan Sands
cdd4f8c7cb Correct bogus module triple specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30 10:48:29 +00:00
Chris Lattner
0de5cad74d LICM does get dead instructions input to it. Instead of sinking them
out of loops, just delete them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 18:22:25 +00:00
Dan Gohman
eaa40ff74e Make IVUsers iterative instead of recursive.
This has the side effect of reversing the order of most of
IVUser's results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112442 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 16:40:03 +00:00
Dan Gohman
2b5258c5f9 Make this test less dependent on register allocation choices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112426 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 14:49:42 +00:00
Dan Gohman
05841638a7 Use exec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112425 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 14:49:00 +00:00
Kalle Raiskila
bd887df8b9 Fix lowering of INSERT_VECTOR_ELT in SPU.
The IDX was treated as byte index, not element index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 12:41:50 +00:00
Bob Wilson
04d6c289ab Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112416 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 05:57:34 +00:00
Chris Lattner
82457d08f9 merge a bunch of shuffle tests into sse2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112398 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:19:04 +00:00
Chris Lattner
c19b9477c9 add some nounwind's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-29 03:07:47 +00:00
Chris Lattner
a5729aae5d fixme accomplished
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 20:40:28 +00:00
Chris Lattner
24faf611a3 fix the buildvector->insertp[sd] logic to not always create a redundant
insertp[sd] $0, which is a noop.  Before:

_f32:                                   ## @f32
	pshufd	$1, %xmm1, %xmm2
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm2, %xmm3
	addss	%xmm1, %xmm0
                                        ## kill: XMM0<def> XMM0<kill> XMM0<def>
	insertps	$0, %xmm0, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

after:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movdqa	%xmm2, %xmm0
	insertps	$16, %xmm3, %xmm0
	ret

The extra movs are due to a random (poor) scheduling decision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112379 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 17:59:08 +00:00
Chris Lattner
3ddcc43040 fix the BuildVector -> unpcklps logic to not do pointless shuffles
when the top elements of a vector are undefined.  This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined.  For example, on:

_Complex float f32(_Complex float A, _Complex float B) {
  return A+B;
}

We used to produce (with SSE2, SSE4.1+ uses insertps):

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$16, %xmm2, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm0
	addss	%xmm1, %xmm0
	pshufd	$16, %xmm0, %xmm1
	movdqa	%xmm2, %xmm0
	unpcklps	%xmm1, %xmm0
	ret

We now produce:

_f32:                                   ## @f32
	movdqa	%xmm0, %xmm2
	addss	%xmm1, %xmm2
	pshufd	$1, %xmm1, %xmm1
	pshufd	$1, %xmm0, %xmm3
	addss	%xmm1, %xmm3
	movaps	%xmm2, %xmm0
	unpcklps	%xmm3, %xmm0
	ret

This implements rdar://8368414


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112378 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 17:28:30 +00:00
Benjamin Kramer
9df0a0a871 Update ocaml test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 10:29:41 +00:00
Chris Lattner
61c70e98ac remove unions from LLVM IR. They are severely buggy and not
being actively maintained, improved, or extended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 04:09:24 +00:00
Chris Lattner
5f88af5376 remove the ABCD and SSI passes. They don't have any clients that
I'm aware of, aren't maintained, and LVI will be replacing their value.
nlewycky approved this on irc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 03:51:24 +00:00
Chris Lattner
7900779543 handle the constant case of vector insertion. For something
like this:

struct S { float A, B, C, D; };

struct S g;
struct S bar() { 
  struct S A = g;
  ++A.B;
  A.A = 42;
  return A;
}

we now generate:

_bar:                                   ## @bar
## BB#0:                                ## %entry
	movq	_g@GOTPCREL(%rip), %rax
	movss	12(%rax), %xmm0
	pshufd	$16, %xmm0, %xmm0
	movss	4(%rax), %xmm2
	movss	8(%rax), %xmm1
	pshufd	$16, %xmm1, %xmm1
	unpcklps	%xmm0, %xmm1
	addss	LCPI1_0(%rip), %xmm2
	pshufd	$16, %xmm2, %xmm2
	movss	LCPI1_1(%rip), %xmm0
	pshufd	$16, %xmm0, %xmm0
	unpcklps	%xmm2, %xmm0
	ret

instead of:

_bar:                                   ## @bar
## BB#0:                                ## %entry
	movq	_g@GOTPCREL(%rip), %rax
	movss	12(%rax), %xmm0
	pshufd	$16, %xmm0, %xmm0
	movss	4(%rax), %xmm2
	movss	8(%rax), %xmm1
	pshufd	$16, %xmm1, %xmm1
	unpcklps	%xmm0, %xmm1
	addss	LCPI1_0(%rip), %xmm2
	movd	%xmm2, %eax
	shlq	$32, %rax
	addq	$1109917696, %rax       ## imm = 0x42280000
	movd	%rax, %xmm0
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112345 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 01:50:57 +00:00
Chris Lattner
3dd08734c1 optimize bitcasts from large integers to vector into vector
element insertion from the pieces that feed into the vector.
This handles a pattern that occurs frequently due to code
generated for the x86-64 abi.  We now compile something like
this:

struct S { float A, B, C, D; };
struct S g;
struct S bar() { 
  struct S A = g;
  ++A.A;
  ++A.C;
  return A;
}

into all nice vector operations:

_bar:                                   ## @bar
## BB#0:                                ## %entry
	movq	_g@GOTPCREL(%rip), %rax
	movss	LCPI1_0(%rip), %xmm1
	movss	(%rax), %xmm0
	addss	%xmm1, %xmm0
	pshufd	$16, %xmm0, %xmm0
	movss	4(%rax), %xmm2
	movss	12(%rax), %xmm3
	pshufd	$16, %xmm2, %xmm2
	unpcklps	%xmm2, %xmm0
	addss	8(%rax), %xmm1
	pshufd	$16, %xmm1, %xmm1
	pshufd	$16, %xmm3, %xmm2
	unpcklps	%xmm2, %xmm1
	ret

instead of icky integer operations:

_bar:                                   ## @bar
	movq	_g@GOTPCREL(%rip), %rax
	movss	LCPI1_0(%rip), %xmm1
	movss	(%rax), %xmm0
	addss	%xmm1, %xmm0
	movd	%xmm0, %ecx
	movl	4(%rax), %edx
	movl	12(%rax), %esi
	shlq	$32, %rdx
	addq	%rcx, %rdx
	movd	%rdx, %xmm0
	addss	8(%rax), %xmm1
	movd	%xmm1, %eax
	shlq	$32, %rsi
	addq	%rax, %rsi
	movd	%rsi, %xmm1
	ret

This resolves rdar://8360454



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 01:20:38 +00:00
Dan Gohman
badcda4afa Completely disable tail calls when fast-isel is enabled, as fast-isel
doesn't currently support dealing with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112341 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28 00:51:03 +00:00
Owen Anderson
a0b59f6bd2 Add a prototype of a new peephole optimizing pass that uses LazyValue info to simplify PHIs and select's.
This pass addresses the missed optimizations from PR2581 and PR4420.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:31:36 +00:00
Bob Wilson
d4bfd54ec2 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:18:17 +00:00
Chris Lattner
11493aa471 tidy up test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:15:21 +00:00
Chris Lattner
58fff61a57 no really, fix the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:05:54 +00:00
Chris Lattner
3dc15ccdb0 fix this test. It's not clear what it's really testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112316 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 23:05:27 +00:00
Chris Lattner
4ece577019 Enhance the shift propagator to handle the case when you have:
A = shl x, 42
...
B = lshr ..., 38

which can be transformed into:
A = shl x, 4
...

iff we can prove that the would-be-shifted-in bits
are already zero.  This eliminates two shifts in the testcase
and allows eliminate of the whole i128 chain in the real example.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112314 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 22:53:44 +00:00
Chris Lattner
29cc0b3660 Implement a pretty general logical shift propagation
framework, which is good at ripping through bitfield
operations.  This generalize a bunch of the existing
xforms that instcombine does, such as 
  (x << c) >> c -> and
to handle intermediate logical nodes.  This is useful for
ripping up the "promote to large integer" code produced by
SRoA.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 22:24:38 +00:00
Chris Lattner
d07ad66791 merge and filecheckize test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 20:44:45 +00:00
Chris Lattner
7673290a96 merge two tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112288 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 20:42:10 +00:00
Chris Lattner
f9d05ab007 teach the truncation optimization that an entire chain of
computation can be truncated if it is fed by a sext/zext that doesn't
have to be exactly equal to the truncation result type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112285 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 20:32:06 +00:00
Chris Lattner
e197fd5182 get this test passing on linux builders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112280 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 18:49:08 +00:00
Chris Lattner
784f333aef Add an instcombine to clean up a common pattern produced
by the SRoA "promote to large integer" code, eliminating
some type conversions like this:

   %94 = zext i16 %93 to i32                       ; <i32> [#uses=2]
   %96 = lshr i32 %94, 8                           ; <i32> [#uses=1]
   %101 = trunc i32 %96 to i8                      ; <i8> [#uses=1]

This also unblocks other xforms from happening, now clang is able to compile:

struct S { float A, B, C, D; };
float foo(struct S A) { return A.A + A.B+A.C+A.D; }

into:

_foo:                                   ## @foo
## BB#0:                                ## %entry
	pshufd	$1, %xmm0, %xmm2
	addss	%xmm0, %xmm2
	movdqa	%xmm1, %xmm3
	addss	%xmm2, %xmm3
	pshufd	$1, %xmm1, %xmm0
	addss	%xmm3, %xmm0
	ret

on x86-64, instead of:

_foo:                                   ## @foo
## BB#0:                                ## %entry
	movd	%xmm0, %rax
	shrq	$32, %rax
	movd	%eax, %xmm2
	addss	%xmm0, %xmm2
	movapd	%xmm1, %xmm3
	addss	%xmm2, %xmm3
	movd	%xmm1, %rax
	shrq	$32, %rax
	movd	%eax, %xmm0
	addss	%xmm3, %xmm0
	ret

This seems pretty close to optimal to me, at least without
using horizontal adds.  This also triggers in lots of other
code, including SPEC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112278 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 18:31:05 +00:00
Bob Wilson
7a9ef44b3b Add alignment arguments to all the NEON load/store intrinsics.
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 17:13:24 +00:00
Owen Anderson
660cab32fe Use LVI to eliminate conditional branches where we've tested a related condition previously. Update tests for this change.
This fixes PR5652.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112270 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 17:12:29 +00:00
Daniel Dunbar
d8d36e61fd X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard to find miscompiles with the integrated assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112250 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 01:30:14 +00:00
Chris Lattner
98b3d3793c filecheckize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112235 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 22:23:39 +00:00
Chris Lattner
681ccf40d7 rename test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 22:20:47 +00:00
Chris Lattner
26dbe7ec18 optimize "integer extraction out of the middle of a vector" as produced
by SRoA.  This is part of rdar://7892780, but needs another xform to
expose this.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112232 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 22:14:59 +00:00
Chris Lattner
e5a1426174 optimize bitcast(trunc(bitcast(x))) where the result is a float and 'x'
is a vector to be a vector element extraction.  This allows clang to
compile:

struct S { float A, B, C, D; };
float foo(struct S A) { return A.A + A.B+A.C+A.D; }

into:

_foo:                                   ## @foo
## BB#0:                                ## %entry
	movd	%xmm0, %rax
	shrq	$32, %rax
	movd	%eax, %xmm2
	addss	%xmm0, %xmm2
	movapd	%xmm1, %xmm3
	addss	%xmm2, %xmm3
	movd	%xmm1, %rax
	shrq	$32, %rax
	movd	%eax, %xmm0
	addss	%xmm3, %xmm0
	ret

instead of:

_foo:                                   ## @foo
## BB#0:                                ## %entry
	movd	%xmm0, %rax
	movd	%eax, %xmm0
	shrq	$32, %rax
	movd	%eax, %xmm2
	addss	%xmm0, %xmm2
	movd	%xmm1, %rax
	movd	%eax, %xmm1
	addss	%xmm2, %xmm1
	shrq	$32, %rax
	movd	%eax, %xmm0
	addss	%xmm1, %xmm0
	ret

... eliminating half of the horribleness.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 21:55:42 +00:00
Chris Lattner
a6140a1444 filecheckize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112225 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 21:51:41 +00:00
Chris Lattner
5333459a1e rename test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 21:50:56 +00:00
Owen Anderson
62efd3b385 Make JumpThreading smart enough to properly thread StrSwitch when it's compiled with clang++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 17:40:24 +00:00
Dan Gohman
6cb8c23db1 Reapply r112091 and r111922, support for metadata linking, with a
fix: add a flag to MapValue and friends which indicates whether
any module-level mappings are being made. In the common case of
inlining, no module-level mappings are needed, so MapValue doesn't
need to examine non-function-local metadata, which can be very
expensive in the case of a large module with really deep metadata
(e.g. a large C++ program compiled with -g).

This flag is a little awkward; perhaps eventually it can be moved
into the ClonedCodeInfo class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 15:41:53 +00:00
Chris Lattner
341fa09a3c Add a hackaround for PR7993 which is causing failures on x86 builders that lack sse2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 06:57:07 +00:00
Chris Lattner
4bbdb4c78c I think enough general codegen bugs are fixed to allow this to work
on random hosts, lets see!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 05:52:42 +00:00
Chris Lattner
8306968c14 implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26 05:51:22 +00:00