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96 Commits

Author SHA1 Message Date
Bradley Smith
9a9fa81c1a [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:07 +00:00
Bradley Smith
86c067813c [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:44:03 +00:00
Bradley Smith
5a09ce9ad1 [ARM64] Rename LR to the UAL-compliant 'X30'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205885 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:59 +00:00
Bradley Smith
37fe6627f6 [ARM64] Rename FP to the UAL-compliant 'X29'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:50 +00:00
Bradley Smith
6af2db2222 [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be zero but should be decoded/disassembled with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205883 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:40 +00:00
Bradley Smith
f797751ca0 [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205882 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:35 +00:00
Bradley Smith
5c73bde178 [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have the top bit of their immediate clear. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205881 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:31 +00:00
Bradley Smith
90c8a50b62 [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205880 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:27 +00:00
Bradley Smith
98422af96f [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205879 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:24 +00:00
Bradley Smith
47c311bafe [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205878 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:20 +00:00
Bradley Smith
8acef8d96d [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205877 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:15 +00:00
Bradley Smith
a8f8d292ca [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:11 +00:00
Bradley Smith
3d41487f0e [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:06 +00:00
Bradley Smith
436fe613fc [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and stores, so the unused register fields are set to all-ones canonically but are recognised with any value. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205874 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:43:01 +00:00
Bradley Smith
dcb9231b8a [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205873 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:56 +00:00
Bradley Smith
84998a1fa9 [ARM64] Remove PrefetchOp and use ARM64PRFM instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205872 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:53 +00:00
Bradley Smith
4be472c874 [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:49 +00:00
Bradley Smith
b336e5d041 [ARM64] Remove ARM64SYS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205870 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:45 +00:00
Bradley Smith
96e05ca4bf [ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembly and assembly. This removes the last users of namespace ARM64SYS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205869 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:42 +00:00
Bradley Smith
fb7edfa9a5 [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:36 +00:00
Bradley Smith
01229fa891 [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. These files are required in the decoder, disassembler and parser, and a layering violation was imminent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205867 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:27 +00:00
Bradley Smith
0fc7d2bdd2 [ARM64] Copy the named immediate operand mapping logic and enums from AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205866 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:16 +00:00
Bradley Smith
a493b7786a [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:11 +00:00
Bradley Smith
a5b549e03c [ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:07 +00:00
Bradley Smith
4580af747e [ARM64] Add missing 1Q -> 1q vector kind alias 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:42:01 +00:00
Bradley Smith
1ff9280e05 [ARM64] Add parsing for vector lists such as {v0.8b-v3.8b} 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205862 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:58 +00:00
Bradley Smith
f5234a2c6c [ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:53 +00:00
Bradley Smith
35b8c724c7 [ARM64] STRHro and STRBro were not being decoded at all. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205860 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:49 +00:00
Bradley Smith
6307036c7c [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205859 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:45 +00:00
Bradley Smith
7ac29214ce [ARM64] Register-offset loads and stores with the 'option' field equal to 00x or 10x are undefined. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205858 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 14:41:38 +00:00
Tim Northover
87a79507fa ARM64: scalarize v1i64 mul operation 
This is the second part of fixing PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205836 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 07:07:02 +00:00
Tim Northover
7db3c63bb2 ARM64: add pattern for <1 x i64> custom not node. 
This should fix PR19367.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205835 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-09 06:55:39 +00:00
Juergen Ributzka
c6a7502a80 [Constant Hoisting][ARM64] Enable constant hoisting for ARM64. 
This implements the target-hooks for ARM64 to enable constant hoisting.

This fixes <rdar://problem/14774662> and <rdar://problem/16381500>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205791 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-08 20:39:59 +00:00
Tim Northover
362090adf5 ARM64: fix fmsub patterns which assumed accum operand was first 
Confusingly, the NEON fmla instructions put the accumulator first but the
scalar versions put it at the end (like the fma lib function & LLVM's
intrinsic).

This should fix PR19345, assuming there's only one issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205758 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-08 12:23:51 +00:00
Jim Grosbach
ba1895c16d Tidy up comments a bit. 
Punctuation, grammar, formatting, etc..

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205749 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 23:47:23 +00:00
Jim Grosbach
8e492b1711 ARM64: Range based for loop in ARM64PromoteConstant pass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205748 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 23:47:21 +00:00
Jim Grosbach
2ed715793d ARM64: Clean up file header comment a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205747 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 23:14:38 +00:00
David Blaikie
b29a2b0c4c MachineInstr: introduce explicit_operands and implicit_operands ranges 
Makes iteration over implicit and explicit machine operands more
explicit (har har). Insipired by code review discussion for r205565.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205680 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-05 22:42:04 +00:00
Tim Northover
4a4d62bfb9 ARM64: handle v1i1 types arising from setcc properly. 
There were several overlapping problems here, and this solution is
closely inspired by the one adopted in AArch64 in r201381.

Firstly, scalarisation of v1i1 setcc operations simply fails if the
input types are legal. This is fixed in LegalizeVectorTypes.cpp this
time, and allows AArch64 code to be simplified slightly.

Second, vselect with such a setcc feeding into it ends up in
ScalarizeVectorOperand, where it's not handled. I experimented with an
implementation, but found that whatever DAG came out was rather
horrific. I think Hao's DAG combine approach is a good one for
quality, though there are edge cases it won't catch (to be fixed
separately).

Should fix PR19335.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205625 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-04 14:49:21 +00:00
Tim Northover
0eb313be18 ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts 
The previous patterns directly inserted FMOV or INS instructions into
the DAG for scalar_to_vector & bitconvert patterns. This is horribly
inefficient and can generated lots more GPR <-> FPR register traffic
than necessary.

It's much better to emit instructions the register allocator
understands so it can coalesce the copies when appropriate.

It led to at least one ISelLowering hack to avoid the problems, which
was incorrect for v1i64 (FPR64 has no dsub). It can now be removed
entirely.

This should also fix PR19331.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205616 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-04 09:03:09 +00:00
Tim Northover
604dff27c9 ARM64: add 128-bit MLA operations to the custom selection code. 
Without this change, the llvm_unreachable kicked in. The code pattern
being spotted is rather non-canonical for 128-bit MLAs, but it can
happen and there's no point in generating sub-optimal code for it just
because it looks odd.

Should fix PR19332.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205615 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-04 09:03:02 +00:00
Craig Topper
84f7f350c3 Make consistent use of MCPhysReg instead of uint16_t throughout the tree. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-04 05:16:06 +00:00
Jim Grosbach
91ba0a9f61 Tidy up. Space before ':' in range-based for loops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205585 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 23:43:26 +00:00
Jim Grosbach
6cd0131b34 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205582 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 23:43:12 +00:00
Lang Hames
89218827c8 [ARM64] Teach the ARM64DeadRegisterDefinition pass to respect implicit-defs. 
When rematerializing through truncates, the coalescer may produce instructions
with dead defs, but live implicit-defs of subregs:
E.g.
  %X1<def,dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32

These instructions are live, and their definitions should not be rewritten.

Fixes <rdar://problem/16492408>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205565 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 20:51:08 +00:00
Tim Northover
27d489f3b2 ARM64: always use i64 for the RHS of shift operations 
Switching between i32 and i64 based on the LHS type is a good idea in
theory, but pre-legalisation uses i64 regardless of our choice,
leading to potential ISel errors.

Should fix PR19294.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205519 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 09:26:16 +00:00
Tim Northover
b642eb5dbc ARM64: don't generate __sincos_stret calls unless on MachO 
This should fix PR19314.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205514 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-03 07:06:13 +00:00
Jim Grosbach
bc413d65a2 Make a few more range-based loops use explicit types. 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205458 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-02 20:21:22 +00:00
Jim Grosbach
bc07242d9b Simplify resolveFrameIndex() signature. 
Just pass a MachineInstr reference rather than an MBB iterator.
Creating a MachineInstr& is the first thing every implementation did
anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205453 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-02 19:28:18 +00:00
Jim Grosbach
b4e30b31e9 Make some range based loop types more explicit. 
No functional change, but more readable code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205451 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-02 19:28:08 +00:00