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13 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
add2076c06 Disable ldc1/sdc1 instructions for mips1 targets. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88887 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-16 04:35:29 +00:00
Bruno Cardoso Lopes
9089ba8e5e A real solution for the first part of PR5445 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86895 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-11 23:09:33 +00:00
Bruno Cardoso Lopes
734516d1f6 Fix PR5445 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86651 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-10 02:35:13 +00:00
Dan Gohman
533297b58d Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-29 18:10:34 +00:00
Bruno Cardoso Lopes
d3bdf19ce7 Added support for fround, fextend and FP_TO_SINT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-05-27 17:23:44 +00:00
Bruno Cardoso Lopes
bdfbb74d34 Removed AFGR32 register class 
Handle odd registers allocation in FGR32.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-03-21 00:05:07 +00:00
Bruno Cardoso Lopes
ea9d4d6ab0 Handle i32->f32 bitconvert results. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54315 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-04 06:44:31 +00:00
Bruno Cardoso Lopes
7030ae7728 Added pattern for floating point zero immediate (avoiding a constant pool 
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54229 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-30 19:00:31 +00:00
Bruno Cardoso Lopes
6d399bdea2 Added floating point lowering for select. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54167 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-29 19:05:28 +00:00
Bruno Cardoso Lopes
85e31e3a53 Added floating point lowering for setcc and brcond. 
Fixed COMM asm directive usage.
ConstantPool using custom FourByteConstantSection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54139 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-28 19:11:24 +00:00
Bruno Cardoso Lopes
7b76da145b Fixe typos and 80 column size problems 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-09 04:45:36 +00:00
Bruno Cardoso Lopes
85e9212fcd fixed 32-bit fp_to_sint pattern 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53192 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-07 19:11:24 +00:00
Bruno Cardoso Lopes
225ca9cdd7 Several changes to Mips backend, experimental fp support being the most 
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-07-05 19:05:21 +00:00