Commit Graph

1275 Commits

Author SHA1 Message Date
728662f9e8 Now that we have the ReturnsTwice function attribute, this method is
obsolete. Check the attribute instead.
<rdar://problem/8031714>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142212 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-17 18:22:52 +00:00
30e6740f2e Modify the mapping from landing pad to call sites to accept more than one call
site.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141226 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:24:35 +00:00
6f500541ea Small refactoring. Cache the FunctionInfo->MBB into a local variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141221 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-05 22:16:11 +00:00
3be654f808 Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21 02:20:46 +00:00
83a8031336 Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 18:22:31 +00:00
4815d56bb2 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:17:40 +00:00
3af7a67629 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-20 03:06:13 +00:00
37fefc20d3 Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:09:48 +00:00
4477d691ed A landingpad instruction is neither folded nor dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138387 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 21:33:05 +00:00
1f6a329f79 Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-12 14:54:45 +00:00
f4ea68fa5a fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137303 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-11 06:26:54 +00:00
497a397f3e Revert r135423.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135454 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 00:28:24 +00:00
1360bc8eb0 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
[take 2]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135423 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 20:55:23 +00:00
272511f518 Revert r133953 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134116 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29 23:50:13 +00:00
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28 19:10:37 +00:00
016c5829a5 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27 22:32:04 +00:00
7cc2b07437 Introduce MachineBranchProbabilityInfo class, which has similar API to
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 20:22:37 +00:00
8a115d5bf4 Remove unused statistical counter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132087 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:55:40 +00:00
233857537f Preserve debug info during iSel by keeping DanglingDebugInfoMap live until end of function.
Patch by Micah Villmow


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131908 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-23 17:44:13 +00:00
5a4b3d8c8f Fix PR9955 by only attaching load memory operands to load instructions and
similarly for stores. Now "make check" passes with the MachineVerifier forced
on with the VerifyCoalescing option!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 23:44:34 +00:00
9c4dae6b0b Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131502 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-17 23:02:10 +00:00
975716af1b Delete unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131430 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 22:19:54 +00:00
62427ae8d3 Track how many insns fast-isel successfully selects as well as how many it
misses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 21:51:07 +00:00
0e00c6c561 Don't do tail calls in a function that call setjmp. The stack might be
corrupted when setjmp returns again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131399 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 03:05:33 +00:00
8265e6ab4f Use array_lengthof. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06 19:50:10 +00:00
6005b875b0 Small syntax cleanup; we don't need to #define constants in C++. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130926 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 16:25:23 +00:00
b686af053e Recommit the fix for rdar://9289512 with a couple tweaks to
fix bugs exposed by the gcc dejagnu testsuite:
1. The load may actually be used by a dead instruction, which
   would cause an assert.
2. The load may not be used by the current chain of instructions,
   and we could move it past a side-effecting instruction. Change
   how we process uses to define the problem away.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 21:59:37 +00:00
63c21deee1 Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",
which broke a couple GCC test suite tests at -O0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21 16:14:46 +00:00
37d38bfbbf SelectBasicBlock is rather slow even when it doesn't do anything; skip the
unnecessary work where possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19 17:01:08 +00:00
685090f598 fix an oversight which caused us to compile the testcase (and other
less trivial things) into a dummy lea.  Before we generated:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	leaq	(%rax), %rax
	ret

now we produce:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	ret

This is part of rdar://9289558



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 17:12:08 +00:00
fd3f635103 Fix rdar://9289512 - not folding load into compare at -O0
The basic issue here is that bottom-up isel is matching the branch
and compare, and was failing to fold the load into the branch/compare
combo.  Fixing this (by allowing folding into any instruction of a
sequence that is selected) allows us to produce things like:


cmpb    $0, 52(%rax)
je      LBB4_2

instead of:

movb    52(%rax), %cl
cmpb    $0, %cl
je      LBB4_2

This makes the generated -O0 code run a bit faster, but also speeds up
compile time by putting less pressure on the register allocator and 
generating less code.

This was one of the biggest classes of missing load folding.  Implementing
this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm)
line count.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 06:35:44 +00:00
8bdc251dc5 split a complex predicate out to a helper function. Simplify two for loops,
which don't need to check for falling off the end of a block *and* end of phi
nodes, since terminators are never phis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 06:03:19 +00:00
a2f45291e1 Added block number and name to isel debug output.
I'm tired of doing this manually for each checkout.
If anyone knows a better way debug isel for non-trivial tests feel
free to revert and let me know how to do it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23 01:38:28 +00:00
9d40193d79 trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:39:05 +00:00
2d76c84514 Generalize the register matching code in DAGISel a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:37:19 +00:00
8ca814c4e0 Merge information about the number of zero, one, and sign bits of live-out
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:25 +00:00
324a24f6aa Add a mechanism for invalidating the LiveOutInfo of a PHI, and use it whenever
a block is visited before all of its predecessors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:16 +00:00
a46cd97818 Track blocks visited in reverse postorder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126377 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:13 +00:00
e1497b9791 Refactor the LiveOutInfo interface into a few methods on FunctionLoweringInfo
and make the actual map private.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:08 +00:00
2dbe2850d0 Have isel visit blocks in reverse postorder rather than an undefined order. This
allows for the information propagated across basic blocks to be merged at phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24 10:00:04 +00:00
4ecc82e592 Roll out r126169 and r126170 in an attempt to fix the selfhost bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 03:24:52 +00:00
92efda7e91 Merge information about the number of zero, one, and sign bits of live-out registers
at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine
phase. This fixes <rdar://problem/8760114>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 00:46:27 +00:00
63a8dae64d Have isel visit blocks in reverse postorder rather than an undefined order. This
allows for the information propagated across basic blocks to be merged at phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 00:46:22 +00:00
68e6beeccc Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-21 23:21:26 +00:00
e9a7ea6865 Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-31 21:38:14 +00:00
b99fdee325 reapply my fix for PR8961 with a tweak to properly handle
multi-instruction sequences like calls.  Many thanks to Jakob for
finding a testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-16 02:27:38 +00:00
ca5f616769 Delete an assignment to ThisBB which isn't needed, and tidy up some
comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-14 22:26:16 +00:00
67d9891690 Set the insertion point correctly for instructions generated by load folding:
they should go *before* the new instruction not after it. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-14 01:33:40 +00:00
358de24dc1 Use an IndexedMap for LiveOutRegInfo to hide its dependence on TargetRegisterInfo::FirstVirtualRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-08 23:10:50 +00:00
c36b7069b4 Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07 23:50:32 +00:00