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a23236c360
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13650 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
a23236c360 Add a few patterns to match allzeros without having to use the fp unit. 
Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 01:26:43 +00:00
Bruno Cardoso Lopes
2e64ae4101 Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move 
a convert pattern close to the instruction definition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 01:26:39 +00:00
Jim Grosbach
8050a61914 ARM parsing and encoding tests. 
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136312 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-28 00:37:03 +00:00
Evan Cheng
5de728cfe1 Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. 
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:22:03 +00:00
Jim Grosbach
ed398468b5 ARM assembly parsing and encoding for USUB16 and USUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136289 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:10:05 +00:00
Jim Grosbach
953e2e81de ARM assembly parsing and encoding for USAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:07:00 +00:00
Kevin Enderby
c37d4bbf1f Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. 
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 23:01:50 +00:00
Jim Grosbach
fc2eb31a3c Clean up tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:35:06 +00:00
Jim Grosbach
addec77b54 ARM assembly parsing and encoding support for USAT and USAT16. 
Use range checked immediate operands for instructions. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:34:17 +00:00
Jim Grosbach
5f33d13da4 ARM assembly parsing and encoding tests for USAD8 and USADA8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136284 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:23:02 +00:00
Jim Grosbach
144da2c8f0 ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136282 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:13:08 +00:00
Jim Grosbach
41438398c1 Fix comment copy/paste-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136281 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:11:41 +00:00
Jim Grosbach
29e85bc728 ARM assembly parsing and encoding tests for UQASX and UQSAX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136280 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:09:30 +00:00
Jim Grosbach
24a541b79f ARM assembly parsing and encoding tests for UQADD16 and UQADD8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:08:14 +00:00
Jim Grosbach
49f2ceddd2 ARM assembly parsing and encoding for UMULL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 22:01:42 +00:00
Jim Grosbach
71725a099e ARM assembly parsing and encoding for UMLAL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:58:11 +00:00
Jim Grosbach
2adba4156b ARM assembly parsing and encoding tests for UMAAL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:53:42 +00:00
Jim Grosbach
f36b0a2ee4 ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:21:59 +00:00
Jim Grosbach
66c8982244 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:20:45 +00:00
Jim Grosbach
fb8989e640 ARM parsing and encoding of SBFX and UBFX. 
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 21:09:25 +00:00
Jim Grosbach
b6854ad2b1 ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:43:44 +00:00
Jim Grosbach
8b3fd56e0f ARM assembly parsing and encoding tests for TST instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:38:58 +00:00
Jim Grosbach
f1ae78af17 ARM assembly parsing and encoding tests for TEQ instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:37:36 +00:00
Owen Anderson
06470311c5 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:29:48 +00:00
Bill Wendling
772fe17a6d Merge the contents from exception-handling-rewrite to the mainline. 
This adds the new instructions 'landingpad' and 'resume'.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136253 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:18:04 +00:00
Jim Grosbach
7e1547ebf7 ARM assembly parsing and encoding for extend instructions. 
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 20:15:40 +00:00
Nick Lewycky
e511186183 Teach the ConstantMerge pass about alignment. Fixes PR10514! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 19:47:34 +00:00
Bruno Cardoso Lopes
cea34e41fa The vpermilps and vpermilpd have different behaviour regarding the 
usage of the shuffle bitmask. Both work in 128-bit lanes without
crossing, but in the former the mask of the high part is the same
used by the low part while in the later both lanes have independent
masks. Handle this properly and and add support for vpermilpd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 00:56:34 +00:00
Devang Patel
26a92003cd It is quiet possible that inlined function body is split into multiple chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136196 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 00:34:13 +00:00
Eric Christopher
28176195a4 Remove these two directories. The tests can be ported to dragonegg if 
they're still wanted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136193 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-27 00:07:56 +00:00
Eric Christopher
e927dc654f Remove test/FrontendC, almost all of the tests have been migrated 
to clang now, the rest are in process (6) or have been deleted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136191 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 23:49:39 +00:00
Jakob Stoklund Olesen
e4709777e3 Eliminate copies of undefined values during coalescing. 
These copies would coalesce easily, but the resulting value would be
defined by a deleted instruction. Now we also remove the undefined value
number from the destination register.

This fixes PR10503.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 23:00:24 +00:00
Benjamin Kramer
25ad783322 Update test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136170 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 22:45:39 +00:00
Benjamin Kramer
162ee5c725 Add a neat little two's complement hack for x86. 
On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can
fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add,
which can be commuted and encoded efficiently.

This code is generated for __builtin_clz and friends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 22:42:13 +00:00
Bruno Cardoso Lopes
4ea496846a Recognize unpckh* masks and match 256-bit versions. The new versions are 
different from the previous 128-bit because they work in lanes.
Update a few comments and add testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 22:03:40 +00:00
Eli Friedman
61cc47e15d Prevent x86-specific DAGCombine from creating nodes with illegal type (which could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136148 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 21:02:58 +00:00
Jim Grosbach
84c93d4bb0 FileCheck'ize test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136135 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 20:49:44 +00:00
Eli Friedman
ce1986bd21 XFAIL this test while I investigate it; it's failing for an unexpected reason. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136131 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 20:41:03 +00:00
Eli Friedman
24f05334e6 Add obvious missing case to switch. PR10497. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136130 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 20:38:49 +00:00
Jim Grosbach
189610f946 ARM diagnostics for ldrexd/stredx out of order paired register operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 18:25:39 +00:00
Jim Grosbach
36711e4a3c ARM parsing and encoding tests for load/store exclusive instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 18:07:21 +00:00
Jim Grosbach
4f6f13db1a ARM assembly parsing and encoding for SWP[B] instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 17:15:11 +00:00
Jim Grosbach
ed8384806e ARM parsing and encoding for SVC instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 16:24:27 +00:00
Jim Grosbach
873db3eeba ARM assembly parsing and encoding tests for SUB instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136089 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 15:44:05 +00:00
Jim Grosbach
a46c658c66 Update ARM STM tests. Fix check: prefix for diagnostic tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 15:41:22 +00:00
Bruno Cardoso Lopes
5d348b4dc4 Add 256-bit isel for movsldup/movshdup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136051 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-26 02:39:32 +00:00
Jim Grosbach
185f92e7d0 ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:32:14 +00:00
Nick Lewycky
5a1cb644c9 Finish adding support for lifetime intrinsics to SROA. Fixes PR10121! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:14:22 +00:00
Jim Grosbach
f49433523e ARM assembly parsing and encoding for SSAT16 instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:09:14 +00:00
Bruno Cardoso Lopes
863bd9d5cf Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128 
This also fixes PR10452

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136004 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 23:05:32 +00:00