Commit Graph

9 Commits

Author SHA1 Message Date
Tom Stellard
fbdd318120 R600/SI: Use the same names for VOP3 operands and encoding fields
This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182283 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 15:02:08 +00:00
Tom Stellard
e340b7728a R600/SI: Use same names for corresponding MUBUF operands and encoding fields
The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178930 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 23:31:44 +00:00
Christian Konig
f4632b58c7 R600/SI: remove GPR*AlignEncode
It's much easier to specify the encoding with tablegen directly.

Signed-off-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 09:46:17 +00:00
Christian Konig
8c0b3a0d31 R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
Those two files got mixed up.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175746 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21 15:16:44 +00:00
Christian Konig
e9ba1830df R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.

This actually fixes a piglit test on SI.

v2: use correct register class in addRegisterClass,
    set special classes as not allocatable
v3: revert setting special classes as not allocateable

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:30 +00:00
Christian Konig
8e4eebcecf R600/SI: replace AllReg_* with [SV]Src_* v2
Mark all the operands that can also have an immediate.

v2: SOFFSET is also an SSrc_32 operand

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:13 +00:00
Christian Konig
305fefbb65 R600/SI: fix VOPC encoding v2
Previously it only worked because of coincident.

v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
    for the unused SRC2

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:07 +00:00
Christian Konig
7c52866a14 R600/SI: move *_Helper definitions to SIInstrFormat.td
This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175351 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-16 11:28:02 +00:00
Tom Stellard
f98f2ce29e Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11 21:25:42 +00:00