Commit Graph

396 Commits

Author SHA1 Message Date
Benjamin Kramer
795740b591 R600: Remove unsafe type punning. No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186196 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 20:18:05 +00:00
Tom Stellard
c9c322cc39 R600/SI: Add support for f64 kernel arguments
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186182 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:15:26 +00:00
Tom Stellard
97781281ca R600/SI: Implement select and compares for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:15:19 +00:00
Tom Stellard
513fc45629 R600/SI: Add fsqrt pattern for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:15:13 +00:00
Tom Stellard
d2442c10f9 R600/SI: Add double precision fsub pattern for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:15:08 +00:00
Tom Stellard
54453c11b4 R600/SI: SI support for 64bit ConstantFP
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186178 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:15:02 +00:00
Tom Stellard
68e1328662 R600/SI: Add initial double precision support for SI
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-12 18:14:56 +00:00
Aaron Ballman
80095e5f8e Replacing an empty switch with its moral equivalent. No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 17:19:22 +00:00
Michel Danzer
a3e39dc705 R600/SI: Initial local memory support
Enough for the radeonsi driver to use it for calculating derivatives.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186012 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 16:37:07 +00:00
Michel Danzer
5b388cac7f R600/SI: Add pattern for the AMDGPU.barrier.local intrinsic
lit test coverage to follow in the next commit.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186011 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 16:36:57 +00:00
Michel Danzer
0a9e22b863 R600/SI: Add intrinsic for retrieving the current thread ID
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 16:36:52 +00:00
Michel Danzer
7740daa8ba R600/SI: Initial support for LDS/GDS instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186009 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 16:36:43 +00:00
Michel Danzer
0a9aaacd72 R600/SI: Add intrinsics for texture sampling with user derivatives
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-10 16:36:36 +00:00
Vincent Lejeune
f2cfef8172 R600: Do not predicated basic block with multiple alu clause
Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.

NOTE: This is a candidate for the stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185943 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 15:03:33 +00:00
Vincent Lejeune
f4bdec2ebe R600: Fix a rare bug where swizzle optimization returns wrong values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185942 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 15:03:25 +00:00
Vincent Lejeune
07bb3f1d0a R600: Fix wrong export reswizzling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185941 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 15:03:19 +00:00
Vincent Lejeune
c6f13db656 R600: Use DAG lowering pass to handle fcos/fsin
NOTE: This is a candidate for the stable branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 15:03:11 +00:00
Vincent Lejeune
f79b9b8593 R600: Print Export Swizzle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-09 15:03:03 +00:00
Craig Topper
365ef0b197 Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185540 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 15:07:05 +00:00
Rafael Espindola
a3863ea2da Remove address spaces from MC.
This is dead code since PIC16 was removed in 2010. The result was an odd mix,
where some parts would carefully pass it along and others would assert it was
zero (most of the object streamer for example).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 15:49:13 +00:00
Chad Rosier
bde84a96ea Add a newline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 21:31:10 +00:00
Vincent Lejeune
c36a8d2b3d R600: Fix an unitialized variable in R600InstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-30 21:44:06 +00:00
Benjamin Kramer
97daabf318 R600: Unbreak GCC build.
operator++ on an enum is not legal. clang happens to accept it anyways, I think
that's a known bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-29 20:04:19 +00:00
Vincent Lejeune
8f9fbd67c3 R600: Support schedule and packetization of trans-only inst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-29 19:32:43 +00:00
Vincent Lejeune
7d1a0d4e3e R600: Bank Swizzle now display SCL equivalent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-29 19:32:29 +00:00
Tom Stellard
74cf767093 R600/SI: Add processor types for each CIK variant
Patch By: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185209 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 20:23:29 +00:00
Tom Stellard
e3d4cbc7d2 R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 15:47:08 +00:00
Tom Stellard
cedcfee405 R600: Add support for GROUP_BARRIER instruction
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 15:46:59 +00:00
Tom Stellard
7e9381951e R600: Add ALUInst bit to tablegen definitions v2
v2:
  - Remove functions left over from a previous rebase.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 15:46:53 +00:00
Tom Stellard
5e48a0e9ae R600: Use new getNamedOperandIdx function generated by TableGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 21:22:18 +00:00
Aaron Watry
f97c7fef52 R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:57 +00:00
Aaron Watry
1842ec4d9f R600/SI: Expand xor v2i32/v4i32
Add test cases for both vector sizes on SI and also add v2i32 test for EG.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184846 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:52 +00:00
Aaron Watry
41f3db569c R600/SI: Expand urem of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UREM produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:46 +00:00
Aaron Watry
e80978f9dd R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:43 +00:00
Aaron Watry
c1fcf01d7f R600/SI: Expand ashr of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:40 +00:00
Aaron Watry
61de9f83cb R600/SI: Expand srl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184841 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:37 +00:00
Aaron Watry
60e6dacd1c R600/SI: Expand shl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184840 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:32 +00:00
Aaron Watry
b8ce77752b R600/SI: Expand or of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184839 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:29 +00:00
Aaron Watry
02ed261f7f R600/SI: Expand mul of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184838 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:26 +00:00
Aaron Watry
e3599ca191 R600/SI: Expand and of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184837 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 13:55:23 +00:00
Tom Stellard
73e44d8ae4 R600/SI: Report unaligned memory accesses as legal for > 32-bit types
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space.  Allowing
unaligned loads/stores for > 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple loads of smaller types.

https://bugs.freedesktop.org/show_bug.cgi?id=65873

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184822 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:39:35 +00:00
Tom Stellard
d67d029b6d R600: Add support for i32 loads from the constant address space on Cayman
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:39:30 +00:00
Tom Stellard
fa57da12f7 R600/SI: Add support for v4i32 and v4f32 kernel args
Tested-By: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:39:25 +00:00
Tom Stellard
1cb1107c66 R600: Fix typo in R600Schedule.td
This should only make a difference in programs that use a lot of the
vector ALU instructions like BFI_INT and BIT_ALIGN.  There is a slight
improvement in the phatk bitcoin mining kernel with this patch on
Evergreen (vector size == 1):

Before:
1173 Instruction Groups / 9520 dwords

After:
1167 Instruction Groups / 9510 dwords

Reviewed-by: Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-25 02:39:20 +00:00
Aaron Watry
6c4b8fe9dd R600: Fix spelling error in comment
our -> or

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-24 16:57:57 +00:00
Tom Stellard
4010e43810 R600/SI: Expand sub for v2i32 and v4i32 for SI
Also add a v2i32 test to the existing v4i32 test.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184482 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 21:55:37 +00:00
Tom Stellard
fe91c515d7 R600/SI: Expand add for v2i32 and v4i32
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184481 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 21:55:30 +00:00
Tom Stellard
eb3aa070c9 R600: Expand v2i32 load/store instead of custom lowering
The custom lowering causes llc to crash with a segfault.

Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184480 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-20 21:55:23 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
Matt Arsenault
ad966ea7a8 Move StructurizeCFG out of R600 to generic Transforms.
Register it with PassManager

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 20:18:24 +00:00