Commit Graph

1126 Commits

Author SHA1 Message Date
Kaelyn Takata
c39b659b89 Remove the use of "%e" as it is not a valid expansion like "%t".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205991 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 21:55:58 +00:00
Kevin Enderby
e7ef041ba4 For the ARM integrated assembler add checking of the
alignments on vld/vst instructions.  And report errors for
alignments that are not supported.

While this is a large diff and an big test case, the changes
are very straight forward.  But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.

FYI, re-committing this with a tweak so MemoryOp's default
constructor is trivial and will work with MSVC 2012. Thanks
to Reid Kleckner and Jim Grosbach for help with the tweak.

rdar://11312406


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205986 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 20:18:58 +00:00
Reid Kleckner
6a6b4d5dfa Revert "For the ARM integrated assembler add checking of the alignments on vld/vst instructions. And report errors for alignments that are not supported."
It doesn't build with MSVC 2012, because MSVC doesn't allow union
members that have non-trivial default constructors.  This change added
'SMLoc AlignmentLoc' to MemoryOp, which made MemoryOp's default ctor
non-trivial.

This reverts commit r205930.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205944 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-10 00:52:14 +00:00
Kevin Enderby
34d14bb534 For the ARM integrated assembler add checking of the
alignments on vld/vst instructions.  And report errors for
alignments that are not supported.

While this is a large diff and an big test case, the changes
are very straight forward.  But pretty much had to touch
all vld/vst instructions changing the addrmode to one of the
new ones that where added will do the proper checking for
the specific instruction.

rdar://11312406


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205930 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 21:32:59 +00:00
Kevin Enderby
9143956488 Fix the ARM VLD3 (single 3-element structure to all lanes)
size 16 double-spaced registers instruction printing.

This:
	vld3.16 {d0[], d2[], d4[]}, [r4]!

was being printed as:

	vld3.16	{d0[], d1[], d2[]}, [r4]!

rdar://16531387


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205779 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-08 18:00:52 +00:00
Stepan Dyatkovskiy
148692bafe Fix for PR18921 (LDRD/STRD part)::
Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td
Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now.
Added new tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 10:17:56 +00:00
Stepan Dyatkovskiy
a669270654 Fixed register class in STRD instruction for Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-04 08:14:13 +00:00
Saleem Abdulrasool
5fe5b3dcc8 ARM: update even more tests
More updating of tests to be explicit about the target triple rather than
relying on the default target triple supporting ARM mode.

Indicate to lit that object emission is not yet available for Windows on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205545 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 17:35:22 +00:00
Saleem Abdulrasool
27b1252c13 ARM: fixup more tests to specify the target more explicitly
This changes the tests that were targeting ARM EABI to explicitly specify the
environment rather than relying on the default.  This breaks with the new
Windows on ARM support when running the tests on Windows where the default
environment is no longer EABI.

Take the opportunity to avoid a pointless redirect (helps when trying to debug
with providing a command line invocation which can be copy and pasted) and
removing a few greps in favour of FileCheck.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 16:01:44 +00:00
Stepan Dyatkovskiy
37e5cfa4aa PR19320:
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP.
It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205524 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-03 11:29:15 +00:00
Stepan Dyatkovskiy
3fed2f133c Recommitted fix for PR18931, with extended tests set.
Issue subject: Crash using integrated assembler with immediate arithmetic

Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205094 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 13:12:40 +00:00
Rafael Espindola
224dbf4aec Completely rewrite ELFObjectWriter::RecordRelocation.
I started trying to fix a small issue, but this code has seen a small fix too
many.

The old code was fairly convoluted. Some of the issues it had:

* It failed to check if a symbol difference was in the some section when
  converting a relocation to pcrel.
* It failed to check if the relocation was already pcrel.
* The pcrel value computation was wrong in some cases (relocation-pc.s)
* It was missing quiet a few cases where it should not convert symbol
  relocations to section relocations, leaving the backends to patch it up.
* It would not propagate the fact that it had changed a relocation to pcrel,
  requiring a quiet nasty work around in ARM.
* It was missing comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 06:26:49 +00:00
Christian Pirker
1f072c36d0 Add ARM big endian Target (armeb, thumbeb)
Reviewed at http://llvm-reviews.chandlerc.com/D3095



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205007 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-28 14:35:30 +00:00
Stepan Dyatkovskiy
fee5d23404 Rejected r204899 and r204900 due to remaining test failures on cmake-llvm-x86_64-linux buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204901 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 08:38:18 +00:00
Stepan Dyatkovskiy
a36286cb49 Fixed test for r204899 (pr18931 fix)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 08:20:26 +00:00
Stepan Dyatkovskiy
fccc6901d6 Fix for pr18931: Crash using integrated assembler with immediate arithmetic
Fix description:
Expressions like 'cmp r0, #(l1 - l2) >> 3' could not be evaluated on asm parsing stage,
since it is impossible to resolve labels on this stage. In the end of stage we still have
expression (MCExpr).
Then, when we want to encode it, we expect it to be an immediate, but it still an expression.
Patch introduces a Fixup (MCFixup instance), that is processed after main encoding stage.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 07:49:39 +00:00
Jiangning Liu
09b4588309 ARM: raise error message when complex SO expressions can't really be
solved as a constant at compilation time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204898 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-27 07:42:58 +00:00
Kevin Enderby
9efa4ff901 Fix the ARM VST4 (single 4-element structure from one lane)
size 16 double-spaced registers instruction printing.

This:
	vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!

was being printed as:

	vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!

rdar://16435096


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-26 19:35:40 +00:00
Rafael Espindola
2236f9348d Teach llvm-readobj to print human friendly description of reserved sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204584 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-24 05:00:34 +00:00
Saleem Abdulrasool
7afe0000f6 ARM IAS: properly handle function entries in .thumb
When a label is parsed, check if there is type information available for the
label.  If so, check if the symbol is a function.  If the symbol is a function
and we are in thumb mode and no explicit thumb_func has been emitted, adjust the
symbol data to indicate that the function definition is a thumb function.

The application of this inferencing is improved value handling in the object
file (the required thumb bit is set on symbols which are thumb functions).  It
also helps improve compatibility with binutils.

The one complication that arises from this handling is the MCAsmStreamer.  The
default implementation of getOrCreateSymbolData in MCStreamer does not support
tracking the symbol data.  In order to support the semantics of thumb functions,
track symbol data in assembly streamer.  Although O(n) in number of labels in
the TU, this is already done in various other streamers and as such the memory
overhead is not a practical concern in this scenario.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-22 19:26:18 +00:00
Jiangning Liu
705e53e2aa This reverts commit r203762, "ARM: support emission of complex SO expressions".
The commit r203762 introduced silent failure for complext SO expression, and it's even worse than compiler crash.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204427 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-21 02:51:01 +00:00
Greg Fitzgerald
aff0ab4e7c llvm-objdump output hex to match binutils' objdump
Patch by Ted Woodward

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204409 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 22:55:15 +00:00
Saleem Abdulrasool
9320b807aa Reapply 'ARM IAS: support .thumb_set'
Re-apply the change after it was reverted to do conflicts due to another change
being reverted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204306 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 06:05:33 +00:00
Rafael Espindola
025e94d7dc Revert "Add back r203962, r204028 and r204059."
This reverts commit r204178.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204203 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-19 00:13:43 +00:00
Rafael Espindola
4af106a677 Add back r203962, r204028 and r204059.
This reverts commit r204137.

This includes a fix for handling aliases of aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204178 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 20:40:38 +00:00
Alexander Kornienko
8a99824c5a Revert r203962 and two revisions depending on it: r204028 and r204059.
The revision I'm reverting breaks handling of transitive aliases. This blocks us
and breaks sanitizer bootstrap:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/2651
(and checked locally by Alexey).

This revision is the result of:

  svn merge -r204059:204058 -r204028:204027 -r203962:203961 .

+ the regression test added to test/MC/ELF/alias.s

Another way to reproduce the regression with clang:
  $ cat q.c
  void a1();
  void a2() __attribute__((alias("a1")));
  void a3() __attribute__((alias("a2")));
  void a1() {}

  $ ~/work/llvm-build/bin/clang-3.5-good -c q.c && mv q.o good.o && \
      ~/work/llvm-build/bin/clang-3.5-bad -c q.c && mv q.o bad.o && \
      objdump -t good.o bad.o

    good.o:     file format elf64-x86-64

    SYMBOL TABLE:
    0000000000000000 l    df *ABS*  0000000000000000 q.c
    0000000000000000 l    d  .text  0000000000000000 .text
    0000000000000000 l    d  .data  0000000000000000 .data
    0000000000000000 l    d  .bss   0000000000000000 .bss
    0000000000000000 l    d  .comment       0000000000000000 .comment
    0000000000000000 l    d  .note.GNU-stack        0000000000000000 .note.GNU-stack
    0000000000000000 l    d  .eh_frame      0000000000000000 .eh_frame
    0000000000000000 g     F .text  0000000000000006 a1
    0000000000000000 g     F .text  0000000000000006 a2
    0000000000000000 g     F .text  0000000000000006 a3



    bad.o:     file format elf64-x86-64

    SYMBOL TABLE:
    0000000000000000 l    df *ABS*  0000000000000000 q.c
    0000000000000000 l    d  .text  0000000000000000 .text
    0000000000000000 l    d  .data  0000000000000000 .data
    0000000000000000 l    d  .bss   0000000000000000 .bss
    0000000000000000 l    d  .comment       0000000000000000 .comment
    0000000000000000 l    d  .note.GNU-stack        0000000000000000 .note.GNU-stack
    0000000000000000 l    d  .eh_frame      0000000000000000 .eh_frame
    0000000000000000 g     F .text  0000000000000006 a1
    0000000000000000 g     F .text  0000000000000006 a2
    0000000000000000 g       .text  0000000000000000 a3




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204137 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-18 10:36:11 +00:00
Saleem Abdulrasool
5b5e5abd20 ARM IAS: support .thumb_set
This performs the equivalent of a .set directive in that it creates a symbol
which is an alias for another symbol or value which may possibly be yet
undefined.  This directive also has the added property in that it marks the
aliased symbol as being a thumb function entry point, in the same way that the
.thumb_func directive does.

The current implementation fails one test due to an unrelated issue.  Functions
within .thumb sections are not marked as thumb_func.  The result is that
the aliasee function is not valued correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204059 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-17 17:13:54 +00:00
Oliver Stannard
d463c7e74e Generalise assembly tests to not rely on anonymous symbol names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203909 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-14 09:10:26 +00:00
Saleem Abdulrasool
0ed4ef85a8 ARM: support emission of complex SO expressions
Support to the IAS was added to actually parse and handle the complex SO
expressions.  However, the object file lowering was not updated to compensate
for the fact that the shift operand may be an absolute expression.

When trying to assemble to an object file, the lowering would fail while
succeeding when emitting purely assembly.  Add an appropriate test.

The test case is inspired by the test case provided by Jiangning Liu who also
brought the issue to light.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203762 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-13 07:02:41 +00:00
Duncan P. N. Exon Smith
ac4c4a8844 ARM: Make .unreq directives case-insensitive
Be case-insensitive when processing .unreq directives.

Patch by Lin Zuojian!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203251 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 16:16:52 +00:00
Saleem Abdulrasool
ec1c80576d ARM IAS: support .align without parameters
.align is handled specially on certain targets.  .align without any parameters
on ARM indicates a default alignment (4).  Handle the special case in the target
parser, but fall back to the generic parser for the normal version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 17:45:32 +00:00
Saleem Abdulrasool
be66089390 ARM IAS: support .short and .hword
This adds support for the .short and its alias .hword for adding literal values
into the object file.  This is similar to the .word directive, however, rather
than inserting a value of 4 bytes, adds a 2-byte value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201968 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 06:22:09 +00:00
Kevin Enderby
4959a2d878 Fix the arm assembler so that this malformed instruction:
ldrd r6, r7 [r2, #15]
simply gives an error and does not triggers an assertion.

As Jim points out, the diagnostic is really strange here,
but fixing that would be more complicated. The missing
comma results in the parser expecting a construct like r2[2],
which is the vector index thing the error message is talking
about. That's not what the user intended, though, and there's
nothing else in the instruction that looks at all like a vector.
Yet more fallout from not having a real parser here and trying
to do context-free generic matching for addressing modes.

rdar://15097243


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201531 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 21:45:27 +00:00
Saleem Abdulrasool
1edea19210 ARM IAS: (partially) support .arch_extension directive
This adds a partial implementation of the .arch_extension directive to the
integrated ARM assembler.  There are a number of limitations to this
implementation arising from the target backend support rather than the
implementation itself.  Namely, iWMMXT (v1 and v2), Maverick, and XScale support
is not present in the ARM backend.  Currently, there is no check for A-class
only (needed for virt), and no ARMv6k detection (needed for os and sec).  The
remainder of the extensions are fully supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201471 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 00:16:41 +00:00
Jim Grosbach
75bf592807 Tidy up a bit. Formatting only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 20:48:41 +00:00
Jim Grosbach
0c2ff8cbfd ARM: Thumb2 LDR(literal) can target SP.
Fix a slightly overzealous destination register restriction for the
'without .w' alias. Add some explicit testcases.

rdar://16033140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201173 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 20:48:39 +00:00
Saleem Abdulrasool
91ec991b45 ARM: change attribute tests to use parsed form
This makes the tests more readable by using the -arm-attributes decoding support
in llvm-readobj since that is now available.  Change the invocation commands to
be similar to other test and use a more precise triple (the tests only require
ARM EABI support).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201029 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-08 23:17:02 +00:00
Renato Golin
703197fc94 Remove -arm-disable-ehabi option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200988 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-07 20:12:49 +00:00
Logan Chien
575c4addce ARM: Resolve thumb_bl fixup in same MCFragment.
In Thumb1 mode, bl instruction might be selected for branches between
basic blocks in the function if the offset is greater than 2KB.
However, this might cause SEGV because the destination symbol
is not marked as thumb function and the execution mode will be reset
to ARM mode.

Since we are sure that these symbols are in the same data fragment, we
can simply resolve these local symbols, and don't emit any relocation
information for this bl instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 14:15:16 +00:00
Saleem Abdulrasool
09f38a0ef1 ARM IAS: support .object_arch
The .object_arch directive indicates an alternative architecture to be specified
in the object file.  The directive does *not* effect the enabled feature bits
for the object file generation.  This is particularly useful when the code
performs runtime detection and would like to indicate a lower architecture as
the requirements than the actual instructions used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:46:41 +00:00
Saleem Abdulrasool
7a38b33dec ARM IAS: support .movsp
.movsp is an ARM unwinding directive that indicates to the unwinder that a
register contains an offset from the current stack pointer.  If the offset is
unspecified, it defaults to zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200449 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:46:24 +00:00
Saleem Abdulrasool
2c9ed5d050 ARM: suuport .tlsdescseq directive
This enhances the ARMAsmParser to handle .tlsdescseq directives.  This is a
slightly special relocation.  We must be able to generate them, but not consume
them in assembly.  The relocation is meant to assist the linker in generating a
TLS descriptor sequence.  The ELF target streamer is enhanced to append
additional fixups into the current segment and that is used to emit the new
R_ARM_TLS_DESCSEQ relocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200448 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:02:47 +00:00
Saleem Abdulrasool
4747d6b0a5 ARM: support TLS descriptor relocations
Add support for tlsdesc relocations which are part of the ABI, marked as
experimental.  These relocations permit the linker to perform TLS reference
optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200447 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:02:38 +00:00
Saleem Abdulrasool
9629ad3005 ARM: support tlscall relocations
This adds support for TLS CALL relocations.  TLS CALL relocations are used to
indicate to the linker to generate appropriate entries to resolve TLS references
via an appropriate function invocation (e.g. __tls_get_addr(PLT)).

In order to accomodate the linker relaxation of the TLS access model for the
references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete.
This requires that the partial inplace value is also incomplete (i.e. 0).  We
simply avoid the offset value calculation at the time of the fixup adjustment in
the ARM assembler backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200446 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-30 04:02:31 +00:00
Renato Golin
3fca788967 Enable EHABI by default
After all hard work to implement the EHABI and with the test-suite
passing, it's time to turn it on by default and allow users to
disable it as a work-around while we fix the eventual bugs that show
up.

This commit also remove the -arm-enable-ehabi-descriptors, since we
want the tables to be printed every time the EHABI is turned on
for non-Darwin ARM targets.

Although MCJIT EHABI is not working yet (needs linking with the right
libraries), this commit also fixes some relocations on MCJIT regarding
the EH tables/lib calls, and update some tests to avoid using EH tables
when none are needed.

The EH tests in the test-suite that were previously disabled on ARM
now pass with these changes, so a follow-up commit on the test-suite
will re-enable them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-29 11:50:56 +00:00
David Woodhouse
634295bcb6 Tests for mode switching
1. test that inlineasm works
2. test that relaxable instructions are re-encoded in the correct mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 23:13:30 +00:00
Mark Seaborn
66aefa805b ARM MC: Fix the initial DWARF CFI unwind info at the start of a function
This brings MC into line with GNU 'as' on ARM, and it brings the ARM
target into line with most other LLVM targets, which declare the
initial CFI state with addInitialFrameState().

Without this, functions generated with .cfi_startproc/endproc on ARM
will tend to cause GDB to abort with:
  gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule.

I've also tested this by comparing the output of "readelf -w" on the
object files produced by llvm-mc and gas when given the .s file added
here.

This change is part of addressing PR18636.

Differential Revision: http://llvm-reviews.chandlerc.com/D2597

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200255 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-27 22:38:14 +00:00
Saleem Abdulrasool
283b40e4d4 MC: fix test locations/name
Placed the MC variant diagnostics in the wrong directory accidentally.  Move
them into their respective architecture specific directories.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200161 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 22:55:02 +00:00
Saleem Abdulrasool
4fefc13b5e ARM: improve diagnostics for .word directive
If a complex expression was passed to the .word directive and the first part of
the directive failed to parse, a secondary diagnostic would be produced that
would clutter the error diagnostics.  Improve the diagnostics by consuming the
remainder of the statement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200160 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 22:29:50 +00:00
Artyom Skrobov
85ae0340ba Reverting r199886 (Prevent repetitive warnings for unrecognized processors and features)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200083 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-25 16:56:18 +00:00