Commit Graph

9963 Commits

Author SHA1 Message Date
Elena Demikhovsky
b0a3627443 AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP packed instructions, added encoding tests for them.
By Robert Khazanov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203098 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 08:45:30 +00:00
Elena Demikhovsky
f4623cee34 AVX-512: fixed comressed displacement - by Robert Khazanov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203096 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 08:15:35 +00:00
Yaron Keren
7bc835b7bf Cleaning up two more pre-Visual C++ 2012 build hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203093 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 08:05:43 +00:00
Chandler Carruth
f4ec8bfaec [Layering] Move DebugInfo.h into the IR library where its implementation
already lives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203046 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 00:46:21 +00:00
Cameron McInally
f3ff7c32f7 Lower AVX v4i64->v4i32 truncate to one shuffle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202996 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 19:41:16 +00:00
Reid Kleckner
a9a43d01f2 MS asm: Attempt to parse variables followed by a bracketed displacement
This is required to include MSVC's <atomic> header, which we do now in
LLVM.

Tests forthcoming in Clang, since that's where we test semantic inline
asm changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 17:57:01 +00:00
Saleem Abdulrasool
86e85c1115 X86: 80-column
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 17:11:46 +00:00
Chandler Carruth
4bbfbdf7d7 [Modules] Move CallSite into the IR library where it belogs. It is
abstracting between a CallInst and an InvokeInst, both of which are IR
concepts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202816 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 11:01:28 +00:00
Chandler Carruth
bd7cba0d81 [Modules] Move GetElementPtrTypeIterator into the IR library. As its
name might indicate, it is an iterator over the types in an instruction
in the IR.... You see where this is going.

Another step of modularizing the support library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202815 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 10:40:04 +00:00
Reid Kleckner
4e43e1e686 MC: Fix Intel assembly parser for [global + offset]
We were dropping the displacement on the floor if we also had some
immediate offset.

Should fix PR19033.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 00:33:17 +00:00
Benjamin Kramer
d628f19f5d [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
Remove the old functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 12:27:27 +00:00
Elena Demikhovsky
a9fe27ffb3 AVX-512: Fixed extract_vector_elt for v8i1 vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202624 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 09:19:44 +00:00
Craig Topper
629b96cb4f Switch all uses of LLVM_OVERRIDE to just use 'override' directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 09:09:27 +00:00
Craig Topper
4eb03f049e Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 08:08:51 +00:00
Evgeniy Stepanov
2c4b1c4853 X86Operand is extracted into individual header.
X86Operand is extracted into individual header, because it allows to create an
arbitrary memory operand and append it to MCInst. It'll be reused in X86 inline
assembly instrumentation.

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 12:28:07 +00:00
Craig Topper
74be63b014 [X86] Fix Uses/Defs lists for INS, OUTS, SCAS, CMPS, LODS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 05:08:25 +00:00
Craig Topper
7e992687ad [X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 04:27:00 +00:00
Craig Topper
956ef7f165 [X86] Add RAX/EAX/AX/AL Uses/Defs to the absolute memory location move instructions. Patch by Florian Lukas with some additional instructions fixed by me. Fixes PR18975.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202345 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 04:07:57 +00:00
Quentin Colombet
685b0d9315 Lower unsigned vsetcc to psubus in certain cases
The current approach to lower a vsetult is to flip the sign bit of the
operands, swap the operands and then use a (signed) pcmpgt.  psubus (unsigned
saturating subtract) can be used to emulate a vsetult more efficiently:

+    case ISD::SETULT: {
+      // If the comparison is against a constant we can turn this into a
+      // setule.  With psubus, setule does not require a swap.  This is
+      // beneficial because the constant in the register is no longer
+      // destructed as the destination so it can be hoisted out of a loop.

I also enable lowering via psubus in a few other cases where it's clearly
beneficial: setule and setuge if minu/maxu cannot be used.
    
rdar://problem/14338765

Patch by Adam Nemet <anemet@apple.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202301 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 21:39:12 +00:00
Craig Topper
ecb903c1b5 [x86] Add same itinerary to SYSEXIT64 as SYSEXIT for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202240 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:50:27 +00:00
Craig Topper
9262808ecd [x86] Remove some unused instruction format classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202234 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:06:38 +00:00
Craig Topper
df24b19e45 [x86] Simplify disassembler code slightly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202233 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 06:01:21 +00:00
Quentin Colombet
b55c398992 [X86][SchedModel] Add missing scheduling model for SSE related instructions.
The patch defines new or refines existing generic scheduling classes to match
the behavior of the SSE instructions.
It also maps those scheduling classes on the related SSE instructions.

<rdar://problem/15607571>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202065 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 19:33:51 +00:00
Elena Demikhovsky
58423c8f1a AVX-512: Fixed encoding of VPCMPEQ and VPCMPGT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202015 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 10:08:30 +00:00
Elena Demikhovsky
73f1a5fe45 AVX-512: Fixed encoding of VPTESTMQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201980 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-23 14:28:35 +00:00
Juergen Ributzka
94f20bfe6e [Stackmaps] Move the target-independent frame index elimination for stackmaps and patchpoints into target-specific code.
The lowering of the frame index for stackmaps and patchpoints requires some
target-specific magic and should therefore be handled in the target-specific
eliminateFrameIndex method.

This is related to <rdar://problem/16106219>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201904 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-21 23:29:32 +00:00
Craig Topper
46aa7fb720 [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201767 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 07:59:43 +00:00
Elena Demikhovsky
143df776e2 AVX-512: Fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201761 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 07:00:10 +00:00
Elena Demikhovsky
08316a11e4 AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com)
Fixed truncate i32 to i1; a test will be provided in the next commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-20 06:34:39 +00:00
Rafael Espindola
b4aaffffd3 move getNameWithPrefix and getSymbol to TargetMachine.
TargetLoweringBase is implemented in CodeGen, so before this patch we had
a dependency fom Target to CodeGen. This would show up as a link failure of
llvm-stress when building with -DBUILD_SHARED_LIBS=ON.

This fixes pr18900.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201711 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 20:30:41 +00:00
Rafael Espindola
737c9f6005 Add back r201608, r201622, r201624 and r201625
r201608 made llvm corretly handle private globals with MachO. r201622 fixed
a bug in it and r201624 and r201625 were changes for using private linkage,
assuming that llvm would do the right thing.

They all got reverted because r201608 introduced a crash in LTO. This patch
includes a fix for that. The issue was that TargetLoweringObjectFile now has
to be initialized before we can mangle names of private globals. This is
trivially true during the normal codegen pipeline (the asm printer does it),
but LTO has to do it manually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201700 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 17:23:20 +00:00
Cameron McInally
35f15e54a9 Fix AVX512 vector sqrt assembly strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 15:16:09 +00:00
Daniel Jasper
9a92586114 Revert r201622 and r201608.
This causes the LLVMgold plugin to segfault. More information on the
replies to r201608.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 12:26:01 +00:00
Tim Northover
44697f3fc1 X86 CodeGenPrep: sink shufflevectors before shifts
On x86, shifting a vector by a scalar is significantly cheaper than shifting a
vector by another fully general vector. Unfortunately, because SelectionDAG
operates on just one basic block at a time, the shufflevector instruction that
reveals whether the right-hand side of a shift *is* really a scalar is often
not visible to CodeGen when it's needed.

This adds another handler to CodeGenPrepare, to sink any useful shufflevector
instructions down to the basic block where they're used, predicated on a target
hook (since on other architectures, doing so will often just introduce extra
real work).

rdar://problem/16063505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 10:02:43 +00:00
Craig Topper
fa0cf99585 Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 08:25:02 +00:00
Craig Topper
52fb0a59d0 Reduce size of map field in X86 TSFlags since it now requires less bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 07:29:07 +00:00
Craig Topper
75116bc27e Put some of the X86 formats in a more logical order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201645 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 06:59:13 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 05:34:21 +00:00
Rafael Espindola
6880f0e19f Fix PR18743.
The IR
@foo = private constant i32 42

is valid, but before this patch we would produce an invalid MachO from it. It
was invalid because it would use an L label in a section where the liker needs
the labels in order to atomize it.

One way of fixing it would be to just reject this IR in the backend, but that
would not be very front end friendly.

What this patch does is use an 'l' prefix in sections that we know the linker
requires symbols for atomizing them. This allows frontends to just use
private and not worry about which sections they go to or how the linker handles
them.

One small issue with this strategy is that now a symbol name depends on the
section, which is not available before codegen. This is not a problem in
practice. The reason is that it only happens with private linkage, which will
be ignored by the non codegen users (llvm-nm and llvm-ar).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201608 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 22:24:57 +00:00
Rafael Espindola
1836fe5651 Rename a DebugLoc variable to DbgLoc and a DataLayout to DL.
This is quiet a bit less confusing now that TargetData was renamed DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201606 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 22:05:46 +00:00
Tim Northover
d729dfc96e X86: use vpsllvd (& friends) for 16-bit shifts on Haswell
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201558 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 11:15:32 +00:00
Craig Topper
ce3db3cdb2 Add PS prefix to some classes I missed in r201538.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201551 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 08:24:22 +00:00
Craig Topper
17e2af6928 Add a bunch of OpSize32 tags to 64-bit mode only instructions to match their 32-bit mode counterparts for cases where there is also a OpSize16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201550 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 08:18:29 +00:00
Elena Demikhovsky
2e58f4605d AVX-512: Fixed size of mask registers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201546 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 07:52:26 +00:00
Craig Topper
7d2bb38164 Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201538 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-18 00:21:49 +00:00
Craig Topper
3457506fb9 Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201507 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 10:03:43 +00:00
Elena Demikhovsky
e139a1e0e4 AVX-512: implemented zext fron i1 to i16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201502 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 07:29:33 +00:00
Rafael Espindola
56d34914b2 Remove dead code, we already require cmake 2.8.8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201495 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 14:36:26 +00:00
Elena Demikhovsky
f280c65b32 AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201487 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-16 11:34:23 +00:00
Craig Topper
0877c6575a Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-15 07:29:18 +00:00