Commit Graph

2600 Commits

Author SHA1 Message Date
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09 18:37:27 +00:00
Eli Friedman
64a17b309d Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 21:00:31 +00:00
Caitlin Sadowski
5d97ee31bb Added LateParsed property to TableGen attributes.
This patch was written by DeLesley Hutchins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139300 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 17:40:49 +00:00
James Molloy
0d76b19919 Fix warning on windows; use of comparison with bool argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 08:12:01 +00:00
Andrew Trick
22b4c819d4 Fix a use of freed string contents.
Speculatively try to fix our windows testers with a patch I found on the internet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139279 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 05:25:49 +00:00
Andrew Trick
ed968a9a04 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139278 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-08 05:23:14 +00:00
Jim Grosbach
f0eee6eca8 Thumb2 assembly parsing and encoding for LDRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 23:39:14 +00:00
Jim Grosbach
a8307dd1c9 Thumb2 parsing and encoding for LDR(immediate).
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 20:58:57 +00:00
James Molloy
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 19:42:28 +00:00
Joerg Sonnenberger
08708c8ef3 Dependency should be on the output file name, not the dependency file
name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-07 02:12:03 +00:00
David Greene
011dca7fac Make RecordVal Name an Init
Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names.  We'll use this to
provide more programmability in how we name defs and their associated
members.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 20:12:07 +00:00
Kevin Enderby
98f213cd60 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 18:03:03 +00:00
Craig Topper
5ffedb9352 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-02 04:17:54 +00:00
James Molloy
c047dcade5 Fix up r137380 based on post-commit review by Jim Grosbach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-01 18:02:14 +00:00
Evan Cheng
37fefc20d3 Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 19:09:48 +00:00
Craig Topper
3daa5c29d4 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:09:35 +00:00
Kevin Enderby
fff64ca9cf Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 22:06:28 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 23:32:08 +00:00
Craig Topper
113061d39b Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 07:42:00 +00:00
Jim Grosbach
72f39f8436 Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 21:22:15 +00:00
Jim Grosbach
5b81584f74 Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24 17:46:13 +00:00
Caitlin Sadowski
b1aa80bfe4 Thread safety: Adding in an option for variadic expr* array of arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138351 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 18:49:23 +00:00
Eric Christopher
691a4882ed Fix fpimmm->fpimm typo.
Patch by Micah Villmow!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138330 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23 15:42:35 +00:00
Jim Grosbach
c68e927488 Allow non zero_reg explicit values for OptionalDefOperands in aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138073 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 20:33:06 +00:00
Jim Grosbach
f2764c8908 Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 19:53:51 +00:00
Owen Anderson
83e3f67fb6 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
Patch by James Molloy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137830 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-17 17:44:15 +00:00
Jim Grosbach
578071a087 Prefer diagnostics from target predicate in asm matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137742 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-16 20:12:35 +00:00
Bob Wilson
e17a14e2de Avoid evaluating Neon macro arguments more than once by disabling type checks.
It turns out that the use of "__extension__" in these macros was disabling
the expected "incompatible pointer" warnings, so these type checks were not
doing anything anyway.  They introduced a serious bug by evaluating some
macro arguments twice, which is a big problem for arguments with side effects.
I'll have to find another way to get the right type checking.  Radar 9947657.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137680 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:22:56 +00:00
Jim Grosbach
19cb7f491f MCTargetAsmParser target match predicate support.
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 23:03:29 +00:00
Jim Grosbach
47a24ab4d7 Move MatchResultTy enum into base class definition.
No need for it to be redefined as part of every derived target asm parser
class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-15 20:53:08 +00:00
David Greene
0d886401b3 Make Record Name an Init
Use an Init (ultimately a StringInit) to represent the Record name.
This allows the name to be composed by standard TableGen operators.
This will enable us to get rid of the ugly #NAME# hack processing and
naturally replace it with operators.  It also increases flexibility
and power of the TableGen language by allowing record identifiers to
be computed dynamically.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137232 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 18:27:46 +00:00
David Greene
0b18d59435 Add getAsUnquotedString
Add a method to return an Init as an unquoted string.  This primarily
affects StringInit where we return the value without surrounding it
with quotes.

This is in preparation for removing the ugly #NAME# hack and replacing
it with standard TabelGen operators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137231 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-10 18:27:45 +00:00
Owen Anderson
438f68df35 Fix an oversight in the FixedLenDecoderEmitter where we weren't correctly checking the success result of custom decoder hooks on singleton decodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 23:05:23 +00:00
Owen Anderson
51c9805c4b Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 22:48:45 +00:00
Owen Anderson
8d7d2e1238 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09 20:55:18 +00:00
Owen Anderson
6d74631062 Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08 20:42:17 +00:00
Owen Anderson
154c41dbbc LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04 18:24:14 +00:00
Jim Grosbach
7ce057983e ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03 23:50:40 +00:00
Jim Grosbach
e39389a58d ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-02 18:07:32 +00:00
Owen Anderson
cf6039548b Make the FixedLengthDecoderEmitter smart enough to autogenerate decoders for encodings like "let Inst{11-7} = foo;", where the RHS has no bitwidth specifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136660 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01 22:45:43 +00:00
Owen Anderson
5f801ba6ef The FixedLenDecoder needs to gracefully handle failing per-instruction decoder hooks in addition to per-operand decoder hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136645 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01 20:06:49 +00:00
Owen Anderson
7f76baed5e Enhance the fixed length disassembler to better handle operand decoding failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136635 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-01 18:44:37 +00:00
Owen Anderson
eb809f562e Correctly handle scattered operands where the bits of the operand are contiguous, but out of order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 23:01:18 +00:00
David Greene
05bce0beee Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 22:43:06 +00:00
David Greene
b4f4cbd199 Remove a blank line from the top.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136511 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 20:50:18 +00:00
David Greene
78621a851a [AVX] Make DagInits Unique
Make sure DagInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136501 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 19:07:26 +00:00
David Greene
65bf3ca9aa [AVX] Make FieldInit Unique
Make sure FieldInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 19:07:24 +00:00
David Greene
08f71e3e74 [AVX] Make VarListElementInit Unique
Make sure VarListElementInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136499 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 19:07:23 +00:00
David Greene
aa839b8fa3 [AVX] Make VarBitInit Unique
Make sure VarBitInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 19:07:22 +00:00
David Greene
e0be0e361a [AVX] Make VarInit Unique
Make sure VarInits are unique and created only once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29 19:07:21 +00:00