Commit Graph

1692 Commits

Author SHA1 Message Date
Evan Cheng
21037da713 Fix PR2287. Darwin passes mmx values in register in 64-mode, not Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50716 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-06 07:23:50 +00:00
Mon P Wang
63307c335a Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 19:05:59 +00:00
Chris Lattner
b61bfdb56e no need for eh info
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50658 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 18:24:33 +00:00
Dan Gohman
a779a9899a Add AsmPrinter support for emitting a directive to declare that
the code being generated does not require an executable stack.

Also, add target-specific code to make use of this on Linux
on x86. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 00:28:39 +00:00
Evan Cheng
5759f97f50 Select vector shift with non-immediate i32 shift amount operand by first moving the operand into the right register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50619 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-04 09:15:50 +00:00
Evan Cheng
22b942aa4d Add separate intrinsics for MMX / SSE shifts with i32 integer operands. This allow us to simplify the horribly complicated matching code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50601 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-03 00:52:09 +00:00
Chris Lattner
0b11cbacce specify an arch for non-x86 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50576 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-02 15:11:58 +00:00
Bill Wendling
4fd49e4a2f Adding testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50536 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01 18:41:09 +00:00
Chris Lattner
6bf30ab347 don't randomly miscompile seto/setuo just because we are in
ffastmath mode.  This fixes rdar://5902801, a miscompilation
of gcc.dg/builtins-8.c.

Bill, please pull this into Tak.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50523 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-01 07:26:11 +00:00
Arnold Schwaighofer
d2ef523673 Really commit the test checking the argument lowering behaviour on x86-64 :).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50478 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 09:19:47 +00:00
Arnold Schwaighofer
30e62c098b Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.

Initial PowerPC tail call implementation:

Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).  
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if 
  caller and callee are fastcc
  call is a tail call (in tail call position, call followed by ret)
  no variable argument lists or byval arguments
  option -tailcallopt is enabled
Supported:
 * non pic tail calls on linux/darwin
 * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
 * inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.

A test checking the argument lowering behaviour on x86-64 was added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-30 09:16:33 +00:00
Chris Lattner
3fb2968f2f make the vector conversion magic handle multiple results.
We now compile test2/test3 to:

_test2:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	addps	%xmm1, %xmm0
	ret
_test3:
	## InlineAsm Start
	set %xmm0, %xmm1
	## InlineAsm End
	paddd	%xmm1, %xmm0
	ret

as expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50389 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 04:48:56 +00:00
Chris Lattner
41f6259a4b add support for multiple return values in inline asm. This is a step
towards PR2094.  It now compiles the attached .ll file to:

_sad16_sse2:
	movslq	%ecx, %rax
	## InlineAsm Start
	%ecx %rdx %rax %rax %r8d %rdx %rsi
	## InlineAsm End
	## InlineAsm Start
	set %eax
	## InlineAsm End
	ret

which is pretty decent for a 3 output, 4 input asm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50386 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 04:29:54 +00:00
Evan Cheng
8509fcf8eb Another extract_subreg coalescing bug.
e.g.
vr1024<2> extract_subreg vr1025, 2
If vr1024 do not have the same register class as vr1025, it's not safe to coalesce this away. For example, vr1024 might be a GPR32 while vr1025 might be a GPR64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50385 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-29 01:41:44 +00:00
Evan Cheng
8c2f662d84 Add -march=x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 23:31:41 +00:00
Dan Gohman
1d7153976c Update and_ops.ll according to the recent dagcombiner changes.
Add a new test, and_ops_more.ll, which is XFAIL'd, to
record the parts of and_ops.ll that were affected by this
change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50379 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 23:26:22 +00:00
Evan Cheng
9d32f2aacb Test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50377 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-28 22:14:34 +00:00
Chris Lattner
5a09690446 Implement a signficant optimization for inline asm:
When choosing between constraints with multiple options,
like "ir", test to see if we can use the 'i' constraint and
go with that if possible.  This produces more optimal ASM in
all cases (sparing a register and an instruction to load it),
and fixes inline asm like this:

void test () {
  asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14));
}

Previously we would dump "42" into a memory location (which
is ok for the 'm' constraint) which would cause a problem
because the 'c' modifier is not valid on memory operands.

Isn't it great how inline asm turns 'missed optimization'
into 'compile failed'??

Incidentally, this was the todo in 
PowerPC/2007-04-24-InlineAsm-I-Modifier.ll

Please do NOT pull this into Tak.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50315 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-27 00:37:18 +00:00
Nate Begeman
aea6a6f717 Feedback from chris
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50305 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 21:47:35 +00:00
Nate Begeman
d35f8ef175 Add a testcase for the recent "handle variable vector insert elt in mem" patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50303 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 21:26:59 +00:00
Evan Cheng
b3f346fa36 Update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50293 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 20:13:47 +00:00
Evan Cheng
10e864276b Special handling for MMX values being passed in either GPR64 or lower 64-bits of XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50289 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 19:11:04 +00:00
Dan Gohman
23ce502cb7 Remove the code from CodeGenPrepare that moved getresult instructions
to the block that defines their operands. This doesn't work in the
case that the operand is an invoke, because invoke is a terminator
and must be the last instruction in a block.

Replace it with support in SelectionDAGISel for copying struct values
into sequences of virtual registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50279 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 18:27:55 +00:00
Evan Cheng
ee472b1081 MMX argument passing fixes:
On Darwin / Linux x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].                                                                                                                                      
On Darwin / Linux x86-32, v1i64 values are passed in memory.                                                                                                                                                    
On Darwin x86-64, v8i8, v4i16, v2i32 values are passed in XMM[0-7].                                                                                                                                     
On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50257 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 07:56:45 +00:00
Chris Lattner
25453ea49e Loosen up an assertion to allow intrinsics. I really have no
idea what this code (findNonImmUse) does, so I'm only guessing 
that this is the right thing.  It would be really really nice
if this had comments and perhaps switched to SmallPtrSet
(hint hint) :)

This fixes rdar://5886601, a crash on gcc.target/i386/sse4_1-pblendw.c


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50252 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 05:13:01 +00:00
Evan Cheng
2749c72f30 Fix bug in x86 memcpy / memset lowering. If there are trailing bytes not handled by rep instructions, a new memcpy / memset is introduced for them. However, since source / destination addresses are already adjusted, their offsets should be zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50239 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-25 00:26:43 +00:00
Evan Cheng
1e8586d175 New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50229 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-24 20:01:58 +00:00
Dan Gohman
3dc34f682d Add support to codegen for getresult instructions with undef operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50180 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23 20:21:29 +00:00
Anton Korobeynikov
0e9ddde1cf Disable stack realignment for these tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50172 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23 18:25:44 +00:00
Anton Korobeynikov
e44a4b3bd7 Fix test becase ABI stack alignment dropped to 'normal' value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50171 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23 18:25:16 +00:00
Anton Korobeynikov
51a8feea9b Fix test, instruction count is valid only if stack is not realigned
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50170 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-23 18:24:48 +00:00
Dan Gohman
61a9213440 Implement an x86-64 ABI detail of passing structs by hidden first
argument. The x86-64 ABI requires the incoming value of %rdi to
be copied to %rax on exit from a function that is returning a
large C struct.

Also, add a README-X86-64 entry detailing the missed optimization
opportunity and proposing an alternative approach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50075 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-21 23:59:07 +00:00
Chris Lattner
bd381a777b A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49986 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-20 05:52:46 +00:00
Chris Lattner
b15f760cda Not all x86-64 machines have sse3 apparently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49985 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-20 05:47:56 +00:00
Chris Lattner
1ce9e00f8b rename *.llx -> *.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49970 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-19 22:29:10 +00:00
Evan Cheng
8608f2eff2 64-bit atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49949 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-19 02:30:38 +00:00
Evan Cheng
639f493ebf Be more careful with insert_subreg and extract_subreg where either source or destination operand has already been coalesced with another register that's defined by a insert_subreg or extract_subreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49843 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-17 07:58:04 +00:00
Evan Cheng
621d157676 Fix a sub-register indice propagation bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49832 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-17 00:06:42 +00:00
Evan Cheng
03eb38848c Don't forget about sub-register indices when rematting instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49830 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 23:44:44 +00:00
Evan Cheng
9c1e06e187 After reading memory that's already freed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49810 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 20:24:25 +00:00
Evan Cheng
6f0ca06296 Really test what's intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49802 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 18:21:55 +00:00
Evan Cheng
0d4bdde327 Rewrite LiveVariable liveness computation. The new implementation is much simplified. It eliminated the nasty recursive routines and removed the partial def / use bookkeeping. There is also potential for performance improvement by replacing the conservative handling of partial physical register definitions. The code is currently disabled until live interval analysis is taught of the name scheme.
This patch also fixed a couple of nasty corner cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49784 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 09:46:40 +00:00
Dan Gohman
171c11ec93 Add support for the form of the SSE41 extractps instruction that
puts its result in a 32-bit GPR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49762 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 02:32:24 +00:00
Dan Gohman
bcda285fcc Recreate the size SDNode instead of reusing the old one in the x86
memcpy lowering code; this ensures that the size node has the desired
result type. This fixes a regression from r49572 with @llvm.memcpy.i64
on x86-32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49761 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-16 01:32:32 +00:00
Dan Gohman
a630f4ed91 Add movd instructions to move from MMX registers
to 64-bit GPR registers on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49757 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-15 23:55:07 +00:00
Dan Gohman
80792f3dde Treat EntryToken nodes as "passive" so that they aren't added to the
ScheduleDAG; they don't correspond to any actual instructions so they
don't need to be scheduled.

This fixes a bug where the EntryToken was being scheduled multiple
times in some cases, though it ended up not causing any trouble because 
EntryToken doesn't expand into anything. With this fixed the schedulers
reliably schedule the expected number of units, so we can check this
with an assertion.

This requires a tweak to test/CodeGen/X86/loop-hoist.ll because it
ends up getting scheduled differently in a trivial way, though it was
enough to fool the prcontext+grep that the test does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49701 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-15 01:22:18 +00:00
Dan Gohman
63f7ba085f Upgrade these tests for the current intrinsic prototypes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49669 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-14 18:19:18 +00:00
Dale Johannesen
0a6ee6d131 Remove -unwind-tables-optional everywhere, since
this is now the default.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49667 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-14 17:56:54 +00:00
Arnold Schwaighofer
4b5324ad2c This patch corrects the handling of byval arguments for tailcall
optimized x86-64 (and x86) calls so that they work (... at least for
my test cases).

Should fix the following problems:

Problem 1: When i introduced the optimized handling of arguments for
tail called functions (using a sequence of copyto/copyfrom virtual
registers instead of always lowering to top of the stack) i did not
handle byval arguments correctly e.g they did not work at all :).

Problem 2: On x86-64 after the arguments of the tail called function
are moved to their registers (which include ESI/RSI etc), tail call
optimization performs byval lowering which causes xSI,xDI, xCX
registers to be overwritten. This is handled in this patch by moving
the arguments to virtual registers first and after the byval lowering
the arguments are moved from those virtual registers back to
RSI/RDI/RCX.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49584 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 18:11:06 +00:00
Dan Gohman
707e018423 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00