Commit Graph

14 Commits

Author SHA1 Message Date
Stephen Lin
8b2b8a1835 Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.
This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 06:24:09 +00:00
Kristof Beyls
29e05fe7a8 Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
The Printer will now print instructions with the correct alignment specifier syntax, like
    vld1.8  {d16}, [r0:64]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-22 10:01:33 +00:00
Bob Wilson
1c3ef90cab Add codegen support for using post-increment NEON load/store instructions.
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-07 17:43:21 +00:00
Bob Wilson
7d24705f65 Change register allocation order for ARM VFP and NEON registers to put the
callee-saved registers at the end of the lists.  Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases.  Thanks to
Jakob for helping me realize the problem.

Most of this patch is fixing the testsuite.  There are quite a few places
where we're checking for specific registers.  I changed those to wildcards
in places where that doesn't weaken the tests.  The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116055 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 06:15:13 +00:00
Bob Wilson
40ff01a030 Set alignment operand for NEON VLD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-23 21:43:54 +00:00
Bob Wilson
7a9ef44b3b Add alignment arguments to all the NEON load/store intrinsics.
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27 17:13:24 +00:00
Dan Gohman
d4d01154ef Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,
when the type is floating-point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 22:36:46 +00:00
Bob Wilson
02170c0034 Fix tests for Neon load/store intrinsics to match the i8* types expected by
the intrinsics.  The reason for those i8* types is that the intrinsics are
overloaded on the vector type and we don't have a way to declare an intrinsic
where one argument is an overloaded vector type and another argument is a
pointer to the vector element type.  The bitcasts added here will match what
the frontend will typically generate when these intrinsics are used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101840 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:17:16 +00:00
Bob Wilson
0ea38bb939 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 23:54:04 +00:00
Bob Wilson
7708c22baa Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83479 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07 18:09:32 +00:00
Bob Wilson
ec1d81c389 Update NEON struct names to match llvm-gcc changes.
(This is not required for correctness but might help with sanity.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83415 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-06 21:16:19 +00:00
Dan Gohman
fce288fc91 Eliminate more uses of llvm-as and llvm-dis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Bob Wilson
b0abb4dc42 Use vAny type to get rid of Neon intrinsics that differed only in whether
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 05:39:44 +00:00
Bob Wilson
9b600c60af Add tests for new NEON vld instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78264 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-06 00:38:31 +00:00