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3650 Commits

Author SHA1 Message Date
Anton Korobeynikov
ab8fd40403 Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36490 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 20:44:04 +00:00
Dan Gohman
edc1d15984 Fix a typo in a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36485 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 19:40:56 +00:00
Evan Cheng
faa510726f Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36483 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 19:00:32 +00:00
Evan Cheng
8e29b2192b Minor bug. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36473 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 08:24:22 +00:00
Evan Cheng
05350288a6 Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36458 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-26 01:40:09 +00:00
Evan Cheng
6c087e5585 Match MachineFunction::UsedPhysRegs changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36452 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 22:13:27 +00:00
Evan Cheng
505e5510a2 Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36451 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 22:10:09 +00:00
Evan Cheng
ade31f9f07 Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36449 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 21:34:08 +00:00
Evan Cheng
e96f50142e Data structure change to improve compile time (especially in debug mode). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36447 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 19:34:00 +00:00
Evan Cheng
c1a3520580 This was lefted out. Fixed sumarray-dbl. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36445 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 18:33:21 +00:00
Anton Korobeynikov
8b0a8c84da Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part 
will follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36435 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 14:27:10 +00:00
Evan Cheng
24a3cc4c83 Fix for PR1306. 
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36434 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 07:30:23 +00:00
Evan Cheng
92efbfcd2d Clean up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36431 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 07:18:20 +00:00
Chris Lattner
ea84c5ee95 support for >4G stack frames 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36425 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 04:30:24 +00:00
Chris Lattner
a401b1e1c5 support > 4G stack objects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36422 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 04:20:54 +00:00
Chris Lattner
6266c18ea1 allow support for 64-bit stack objects 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36420 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 04:08:28 +00:00
Chris Lattner
964dd86054 Be more careful about folding op(x, undef) when we have vector operands. 
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36413 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-25 00:00:45 +00:00
Bill Wendling
95b3955034 Assertion when using a 1-element vector for an add operation. Get the 
real vector type in this case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36402 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-24 21:13:23 +00:00
Scott Michel
f147a8d56e Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about 
tests always being true in the process.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36387 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-24 01:24:20 +00:00
Dale Johannesen
00d56b96e5 modify per review commentary 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36383 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-23 23:33:31 +00:00
Dale Johannesen
19f5469be4 make EmitAlignment work the way Chris says it should 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36368 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-23 19:58:54 +00:00
Christopher Lamb
95c218a83e PR400 phase 2. Propagate attributed load/store information through DAGs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36356 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-22 23:15:30 +00:00
Lauro Ramos Venancio
2c5c111b6c X86 TLS: Implement review feedback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36318 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-21 20:56:26 +00:00
Reid Spencer
c67bdc288a Revert Christopher Lamb's load/store alignment changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36309 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-21 18:36:27 +00:00
Christopher Lamb
2330e4d4c4 add support for alignment attributes on load/store instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36301 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio
0d3b67809c Allow the lowering of ISD::GLOBAL_OFFSET_TABLE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36290 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio
b3a0417cad Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-20 21:38:10 +00:00
Evan Cheng
f44c72817e VarInfo::UsedBlocks is no longer used. Remove. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36250 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 05:04:38 +00:00
Chris Lattner
61a4c072b9 allow SRL to simplify its operands, as it doesn't demand all bits as input. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36245 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 03:06:49 +00:00
Chris Lattner
ec06e9a670 When replacing a node in SimplifyDemandedBits, if the old node used any 
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36244 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 03:05:22 +00:00
Chris Lattner
0a16a1f738 fix a pasto 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36242 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 03:01:40 +00:00
Evan Cheng
faf05bbaea Don't populate TryAgainList when coalescing only physical registers with virtual registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36240 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 02:30:19 +00:00
Evan Cheng
3fefc182a0 Increment use count of new virtuals created during PHI elimination. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36233 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-18 00:36:11 +00:00
Chris Lattner
8c7d2d56bf Fix a bug in my previous patch, grabbing the shift amount width from the 
wrong operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36223 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 22:53:02 +00:00
Chris Lattner
895c4ab564 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. 
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36221 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 21:14:16 +00:00
Evan Cheng
20b0abc24f Copy coalescing change to prevent a physical register from being pin to a 
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36218 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 20:32:26 +00:00
Evan Cheng
e52eef8e9a Add a register allocation preference field; add a method to compute size of a live interval. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36216 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 20:25:11 +00:00
Evan Cheng
38b7ca6651 Keep track of number of uses within the function per virtual register. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36214 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 20:22:11 +00:00
Chris Lattner
95a5e0507e SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits 
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-17 19:03:21 +00:00
Reid Spencer
9a9203b894 Fix problems in the PartSet lowering having to do with incorrect bit width. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36180 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 22:21:14 +00:00
Anton Korobeynikov
bed2946a96 Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-16 18:10:23 +00:00
Chris Lattner
1c35968d4d disable switch lowering using shift/and. It still breaks ppc bootstrap for 
some reason.  :(  Will investigate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36011 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-14 19:39:41 +00:00
Anton Korobeynikov
e01017bba4 Fix PR1325: Case range optimization was performed in the case it 
shouldn't. Also fix some "latent" bug on 64-bit platforms


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35990 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-14 13:25:55 +00:00
Chris Lattner
3ff981749b disable shift/and lowering to work around PR1325 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35985 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-14 02:26:56 +00:00
Anton Korobeynikov
8085bcfdca Fix PR1323 : we haven't updated phi nodes in good manner :) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35963 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-13 06:53:51 +00:00
Reid Spencer
df41353497 Make sure intrinsics that are lowered to functions make the function weak 
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35956 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 21:53:38 +00:00
Reid Spencer
eeedcb6905 Fix bugs in generated code for part_select and part_set so that llc doesn't 
barf when CBE is run with a program that contains these intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35946 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 13:30:14 +00:00
Reid Spencer
37958093c6 Fix a bug in PartSet. The replacement value needs to be zext or trunc to 
the size of the value, not just zext. Also, give better names to two BBs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35945 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 12:46:33 +00:00
Chris Lattner
3a508c94a6 the result of an inline asm copy can be an arbitrary VT that the register 
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35944 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 06:00:20 +00:00
Chris Lattner
4829b1c6ab fold noop vbitconvert instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35943 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-04-12 05:58:43 +00:00