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c080d6fb3d
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160 Commits

Author SHA1 Message Date
Evan Cheng
c080d6fb3d Lower memcpy with small constant size operand into a series of load / store 
ops.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26195 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-15 01:54:51 +00:00
Evan Cheng
dea7245997 Doh again! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26188 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 23:05:54 +00:00
Evan Cheng
c4f8eee054 Keep to < 80 cols 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26177 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 20:12:38 +00:00
Evan Cheng
ac940ab1bf Missed a break so memcpy cases fell through to memset. Doh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26176 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 19:45:56 +00:00
Evan Cheng
80e89d7d6c Fixed a build breakage. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26175 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 09:11:59 +00:00
Evan Cheng
a03a5dc7ce Rename maxStoresPerMemSet to maxStoresPerMemset, etc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26174 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:38:30 +00:00
Evan Cheng
1db92f947c Expand memset dst, c, size to a series of stores if size falls below the 
target specific theshold, e.g. 16 for x86.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26171 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 08:22:34 +00:00
Chris Lattner
06a248c9b3 now that libcalls don't suck, we can remove this hack 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26164 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-14 05:39:35 +00:00
Jim Laskey
d96185aa62 Rename to better reflect usage (current and planned.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26145 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-13 12:50:39 +00:00
Jim Laskey
ce72b1755f Reorg for integration with gcc4. Old style debug info will not be passed though 
to SelIDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26115 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-11 01:01:30 +00:00
Evan Cheng
cccf1232a6 Get rid of some memory leaks identified by Valgrind 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25960 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 06:49:00 +00:00
Chris Lattner
dc19b70d24 Add initial support for immediates. This allows us to compile this: 
int %rlwnm(int %A, int %B) {
  %C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
  ret int %C
}

into:

_rlwnm:
        or r2, r3, r3
        or r3, r4, r4
        rlwnm r2, r2, r3, 4, 17    ;; note the immediates :)
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25955 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:26:14 +00:00
Chris Lattner
3d81fee851 Initial early support for non-register operands, like immediates 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25952 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-04 02:16:44 +00:00
Chris Lattner
7632e2beb4 remove some #ifdef'd out code, which should properly be in the dag combiner anyway. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25941 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-03 20:13:59 +00:00
Chris Lattner
2223aea6ed Implement matching constraints. We can now say things like this: 
%C = call int asm "xyz $0, $1, $2, $3", "=r,r,r,0"(int %A, int %B, int 4)

and get:

xyz r2, r3, r4, r2

note that the r2's are pinned together.  Yaay for 2-address instructions.

2342 ----------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25893 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-02 00:25:23 +00:00
Chris Lattner
4e4b576e2e Implement simple register assignment for inline asms. This allows us to compile: 
int %test(int %A, int %B) {
  %C = call int asm "xyz $0, $1, $2", "=r,r,r"(int %A, int %B)
  ret int %C
}

into:

 (0x8906130, LLVM BB @0x8902220):
        %r2 = OR4 %r3, %r3
        %r3 = OR4 %r4, %r4
        INLINEASM <es:xyz $0, $1, $2>, %r2<def>, %r2, %r3
        %r3 = OR4 %r2, %r2
        BLR

which asmprints as:

_test:
        or r2, r3, r3
        or r3, r4, r4
        xyz $0, $1, $2      ;; need to print the operands now :)
        or r3, r2, r2
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25878 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 18:59:47 +00:00
Chris Lattner
2cc2f66c25 adjust to changes in InlineAsm interface. Fix a few minor bugs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25865 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-01 01:28:23 +00:00
Chris Lattner
6656dd1a78 Handle physreg input/outputs. We now compile this: 
int %test_cpuid(int %op) {
        %B = alloca int
        %C = alloca int
        %D = alloca int
        %A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
        %Bv = load int* %B
        %Cv = load int* %C
        %Dv = load int* %D
        %x = add int %A, %Bv
        %y = add int %x, %Cv
        %z = add int %y, %Dv
        ret int %z
}

to this:

_test_cpuid:
        sub %ESP, 16
        mov DWORD PTR [%ESP], %EBX
        mov %EAX, DWORD PTR [%ESP + 20]
        cpuid
        mov DWORD PTR [%ESP + 8], %ECX
        mov DWORD PTR [%ESP + 12], %EBX
        mov DWORD PTR [%ESP + 4], %EDX
        mov %ECX, DWORD PTR [%ESP + 12]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 8]
        add %EAX, %ECX
        mov %ECX, DWORD PTR [%ESP + 4]
        add %EAX, %ECX
        mov %EBX, DWORD PTR [%ESP]
        add %ESP, 16
        ret

... note the proper register allocation.  :)

it is unclear to me why the loads aren't folded into the adds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25827 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-31 02:03:41 +00:00
Chris Lattner
04c62c78f4 remove method I just added 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25728 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-28 03:43:09 +00:00
Chris Lattner
4f16e70faa add a new callback 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25727 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-28 03:37:03 +00:00
Nate Begeman
0aed7840ec Implement Promote for VAARG, and allow it to be custom promoted for people 
who don't want the default behavior (Alpha).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25726 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-28 03:14:31 +00:00
Nate Begeman
ee625573b5 Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 21:09:22 +00:00
Chris Lattner
ce7518ce92 initial selectiondag support for new INLINEASM node. Note that inline asms 
with outputs or inputs are not supported yet. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25664 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-26 22:24:51 +00:00
Nate Begeman
acc398c195 First part of bug 680: 
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 18:21:52 +00:00
Evan Cheng
3f23952404 If scheduler choice is the default (-sched=default), use target scheduling 
preference to determine which scheduler to use. SchedulingForLatency ==
Breadth first; SchedulingForRegPressure == bottom up register reduction list
scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25599 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-25 09:12:57 +00:00
Jim Laskey
17d52f7234 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25545 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 13:34:04 +00:00
Evan Cheng
f0f9c90204 Skeleton of the list schedule. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25544 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 08:26:10 +00:00
Evan Cheng
4ef1086749 Factor out more instruction scheduler code to the base class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25532 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 07:01:07 +00:00
Chris Lattner
39a17dd31d Fix bugs lowering stackrestore, fixing 2004-08-12-InlinerAndAllocas.c on 
PPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25522 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-23 05:22:07 +00:00
Chris Lattner
a3818e6f9a Fix a bug in a recent refactor that caused a bunch of programs to miscompile 
or the compiler to crash.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25503 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-21 19:12:11 +00:00
Evan Cheng
a9c2091cd3 Do some code refactoring on Jim's scheduler in preparation of the new list 
scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25493 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-21 02:32:06 +00:00
Chris Lattner
4eebb60f84 If the target doesn't support f32 natively, insert the FP_EXTEND in target-indep 
code, so that the LowerReturn code doesn't have to handle it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25482 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-20 18:38:32 +00:00
Chris Lattner
d12b2d7b5a Temporary work around for a libcall insertion bug: If a target doesn't 
support FSIN/FCOS nodes, do not lower sin/cos to them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25425 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-18 21:50:14 +00:00
Robert Bocchino
4eb2e3a6f4 Support for the insertelement operation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25405 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-17 20:06:42 +00:00
Reid Spencer
0b118206bf For PR411: 
This patch is an incremental step towards supporting a flat symbol table.
It de-overloads the intrinsic functions by providing type-specific intrinsics
and arranging for automatically upgrading from the old overloaded name to
the new non-overloaded name. Specifically:
  llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64
  llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64
  llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64
  llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64
  llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64
New code should not use the overloaded intrinsic names. Warnings will be
emitted if they are used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25366 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-16 21:12:35 +00:00
Nate Begeman
3a04ffbf6d Remove some duplicated code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25313 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-14 03:18:27 +00:00
Nate Begeman
d88fc03602 bswap implementation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25312 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-14 03:14:10 +00:00
Chris Lattner
140d53c99c Compile llvm.stacksave/restore into STACKSAVE/STACKRESTORE nodes, and allow 
targets to custom expand them as they desire.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25273 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-13 02:50:02 +00:00
Chris Lattner
e8f7a4bbee Add "support" for stacksave/stackrestore to the dag isel 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25268 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-13 02:24:42 +00:00
Robert Bocchino
c0f4cd9931 Added selection DAG support for the extractelement operation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25179 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-10 19:04:57 +00:00
Jim Laskey
b2efb853f0 Applied some recommend changes from sabre. The dominate one beginning "let the 
pass manager do it's thing."  Fixes crash when compiling -g files and suppresses
dwarf statements if no debug info is present.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25100 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-04 22:28:25 +00:00
Chris Lattner
9797c5cc3e enable the gep isel opt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24910 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 19:36:36 +00:00
Chris Lattner
3b841e9f52 Lower ConstantAggregateZero into zeros 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24890 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-21 02:43:26 +00:00
Jim Laskey
f5395cee6a Added source file/line correspondence for dwarf (PowerPC only at this point.) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24748 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-16 22:45:29 +00:00
Chris Lattner
86cb643801 Don't lump the filename and working dir together 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24697 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-13 17:40:33 +00:00
Chris Lattner
ac22c83e68 Accept and ignore prefetches for now 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24678 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-12 22:51:16 +00:00
Chris Lattner
3802c2552f Minor tweak to get isel opt 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24663 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-11 09:05:13 +00:00
Chris Lattner
c78b0b740b improve code insertion in two ways: 
1. Only forward subst offsets into loads and stores, not into arbitrary
   things, where it will likely become a load.
2. If the source is a cast from pointer, forward subst the cast as well,
   allowing us to fold the cast away (improving cases when the cast is
   from an alloca or global).

This hasn't been fully tested, but does appear to further reduce register
pressure and improve code.  Lets let the testers grind on it a bit. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24640 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 08:00:12 +00:00
Nate Begeman
cc827e60b6 Fix a crash where ConstantVec nodes were being generated with the wrong 
type when the target did not support them.  Also teach Legalize how to
expand ConstantVecs.

This allows us to generate

_test:
        lwz r2, 12(r3)
        lwz r4, 8(r3)
        lwz r5, 4(r3)
        lwz r6, 0(r3)
        addi r2, r2, 4
        addi r4, r4, 3
        addi r5, r5, 2
        addi r6, r6, 1
        stw r2, 12(r3)
        stw r4, 8(r3)
        stw r5, 4(r3)
        stw r6, 0(r3)
        blr

For:

void %test(%v4i *%P) {
        %T = load %v4i* %P
        %S = add %v4i %T, <int 1, int 2, int 3, int 4>
        store %v4i %S, %v4i * %P
        ret void
}

On PowerPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24633 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-07 19:48:11 +00:00
Nate Begeman
8cfa57b1b4 Teach the SelectionDAG ISel how to turn ConstantPacked values into 
constant nodes with vector types.  Also teach the asm printer how to print
ConstantPacked constant pool entries.  This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.

LCPI1_0:  <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
        .space  4
        .space  4
        .space  4
        .long   1065353216      ; float 1
        .text
        .align  4
        .globl  _foo
_foo:
        lis r2, ha16(LCPI1_0)
        la r2, lo16(LCPI1_0)(r2)
        li r4, 0
        lvx v0, r4, r2
        lvx v1, r4, r3
        vaddfp v0, v1, v0
        stvx v0, r4, r3
        blr

For the llvm code:

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24616 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-06 06:18:55 +00:00