Commit Graph

3544 Commits

Author SHA1 Message Date
Adam Nemet
8dea1c4167 [X86] AVX512: Add vmovntdqa
Along with the corresponding intrinsic and tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 16:39:53 +00:00
Artyom Skrobov
45a31492d5 Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 13:11:35 +00:00
Alp Toker
8aeca44558 Reduce verbiage of lit.local.cfg files
We can just split targets_to_build in one place and make it immutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 22:42:55 +00:00
Sasa Stankovic
49b83e1e76 [mips] Fix a bug for NaCl target - Don't report the error when non-dangerous
load/store is in branch delay slot.

Differential Revision: http://llvm-reviews.chandlerc.com/D4048

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 14:09:28 +00:00
Artyom Skrobov
a8d18fe946 [AArch64] Missing aliases for CMP/CMN [W]SP with no shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 11:10:14 +00:00
Zoran Jovanovic
0c7ac480e2 [mips][mips64r6] Add LDPC instruction
Differential Revision: http://reviews.llvm.org/D3822


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 09:49:51 +00:00
Saleem Abdulrasool
ea3ab85c01 MC: fix text section characteristics for WoA
link.exe requires that the text section has the IMAGE_SCN_MEM_16BIT flag set.
Otherwise, it will treat the function as ARM.  If this occurs, then jumps to the
function will fail, switching from thumb to ARM mode execution.

With this change, it is possible to link using the MSVC linker as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210415 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 03:57:49 +00:00
Alp Toker
2aa472f4bd Re-enable ARM ELF tests
r210408 inadvertently disabled them when X86 is not selected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210412 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 02:46:02 +00:00
Saleem Abdulrasool
e231836fe4 test: move some tests into ARM directory
Rather than requiring ARM support for the ELF tests (which is odd), move the
tests that require ARM into a subdirectory to use lit to disable them if the
support is not present.  Play this game to prevent disabling the ELF tests on
the Windows build bots as they have caught issues in the past with interactions
between various platforms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 01:04:05 +00:00
Saleem Abdulrasool
eb5f5ae200 MC: make ELF .type handling more GNU AS compatible
GAS documents the .type directive as having an optional comma following the key
symbol name when using the STT_<TYPE_IN_UPPER_CASE> form.  However, it treats
the comma as optional in all cases.  This makes the IAS support both forms of
inputs.  Furthermore, the prefixed forms take either the upper case name or the
lower case alias.

The tests are split into two separate sets as the hash character serves as a
comment character on x86, which is tested in the second set by using arm-elf
which uses the at symbol as a comment character.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210407 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-08 00:34:34 +00:00
Alp Toker
3c9b41b949 Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210401 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-07 21:23:09 +00:00
Saleem Abdulrasool
a51acc7631 MC: prevent early DCE of empty sections
Prevent the early elimination of sections in the object writer.  There may be
references to the section itself by other symbols, which may potentially not be
possible to resolve.  ML (Visual Studio's Macro Assembler) also seems to retain
empty sections.

The elimination of symbols and sections which are unused should really occur at
the link phase.  This will not cause any change in the resulting binary, simply
in the generated object files.

The adjustments to the other unit tests account for the fluctuating section
index caused by the appearance of sections which were previously discarded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210373 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-06 21:40:16 +00:00
Rafael Espindola
013321a0f9 Fix a few issues with comdat handling on COFF.
* Section association cannot use just the section name as many
sections can have the same name. With this patch, the comdat symbol in
an assoc section is interpreted to mean a symbol in the associated
section and the mapping is discovered from it.

* Comdat symbols were not being set correctly. Instead we were getting
whatever was output first for that section.

A consequence is that associative sections now must use .section to
set the association. Using .linkonce would not work since it is not
possible to change a sections comdat symbol (it is used to decide if
we should create a new section or reuse an existing one).

This includes r210298, which was reverted because it was asserting
on an associated section having the same comdat as the associated
section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-06 19:26:12 +00:00
Timur Iskhodzhanov
3ad10cfab8 Revert r210298 'Correctly set the comdat symbol on COFF' as it asserts on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210317 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-06 08:18:18 +00:00
Rafael Espindola
d605148d07 Correctly set the comdat symbol on COFF.
We extended the .section syntax to allow multiple sections with the
same name but different comdats, but currently we don't make sure that
the output section has that comdat symbol.

That happens to work with the code llc produces currently because it looks like

.section secName, "dr", one_only, "COMDATSym"
.globl COMDATSym
COMDATSym:
....

but that is not very friendly to anyone coding in assembly or even to
llc once we get comdat support in the IR.

This patch changes the coff object writer to make sure the comdat symbol is
output just after the section symbol, as required by the coff spec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210298 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-05 23:09:25 +00:00
Matheus Almeida
3a2156d1b5 [mips] Fix triple.
Mips2 is a 32-bit architecture.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210254 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-05 12:07:14 +00:00
Hans Wennborg
6248abf28d Don't emit structors for available_externally globals (PR19933)
We would previously assert here when trying to figure out the section
for the global.

This makes us handle the situation more gracefully since the IR isn't
malformed.

Differential Revision: http://reviews.llvm.org/D4022

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210215 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-04 21:04:54 +00:00
Tim Northover
ba735134d7 MachO: move test to ARM directory.
This test specifies an ARM triple, so it needs ARM as a registered
target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209905 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-30 16:01:29 +00:00
Tim Northover
98f8bc9323 MachO: support N_INDR aliases in assembly files.
This makes LLVM create N_INDR aliases (to be resolved by the linker) when
appropriate.

rdar://problem/15125513

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209894 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-30 13:22:59 +00:00
Artyom Skrobov
897fd5f0ed Restore getInvertedCondCode() from the phased-out backend, fixing disassembly for NV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 11:34:50 +00:00
Artyom Skrobov
684122e84e Add missing check when MatchInstructionImpl() reports failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209802 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 11:26:15 +00:00
Zoran Jovanovic
61e341e0bf [mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16
Differential Revision: http://reviews.llvm.org/D3860


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209659 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 14:58:51 +00:00
Zoran Jovanovic
f7744906f0 [mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2
Differential Revision: http://reviews.llvm.org/D3824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-27 12:55:40 +00:00
Tim Northover
29f94c7201 AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:50:23 +00:00
Tim Northover
9105f66d6f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:42:26 +00:00
David Blaikie
1288a3b8e6 DebugInfo: Generalize some tests to handle variations in attribute ordering.
In an effort to fix inlined debug info in situations where the out of
line definition of a function preceeds any inlined usage, the order in
which some attributes are added to subprogram DIEs may change. (in
essence, definition-necessary attributes like DW_AT_low_pc/high_pc will
be added immediately, but the names, types, and other features will be
delayed to module end where they may either be added to the subprogram
DIE or instead reference an abstract definition for those values)

These tests can be generalized to be resilient to this change. 5 or so
tests actually have to be incompatibly changed to cope with this
reordering and will go along with the change that affects the order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209554 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 21:11:46 +00:00
Daniel Sanders
b3fa233048 [mips] Work around inconsistency in llvm-mc's placement of fixup markers
Summary:
Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly
position llvm-mc's fixup placeholders for big-endian.

See PR19836 for full details of the issue. To summarize, the fixup placeholders
do not account for endianness properly and the implementations of
getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset
from different ends of the instruction encoding to compensate.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3889

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209514 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 13:35:24 +00:00
Daniel Sanders
ff87630a77 [mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in MIPS32r6/MIPS64r6
Summary: Depends on D3872

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3891

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209513 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 13:24:08 +00:00
Daniel Sanders
36b0fd51de [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6
Summary:
Instead the system is required to provide some means of handling unaligned
load/store without special instructions. Options include full hardware
support, full trap-and-emulate, and hybrids such as hardware support within
a cache line and trap-and-emulate for multi-line accesses.

MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to
assume that unaligned accesses are 'fast' on the basis that I expect few
hardware implementations will opt for pure-software handling of unaligned
accesses. The ones that do handle it purely in software can override this.

mips64-load-store-left-right.ll has been merged into load-store-left-right.ll

The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has
been fixed and the variables renamed to clarify the units they hold.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209512 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 13:18:02 +00:00
Saleem Abdulrasool
df9a78247a MC: remove unnecessary restriction on tests
Rafael correctly pointed out that the restriction is unnecessary.  Although the
tests are intended to ensure that we dont abort due to an assertion, running the
tests in all modes is better since it also ensures that we dont crash without
assertions.  Always run these tests to ensure that we can handle invalid input
correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-23 02:56:51 +00:00
Tim Northover
e072ed71c8 ARM64: separate load/store operands to simplify assembler
This changes ARM64 to use separate operands for each component of an
address, and look for separate '[', '$Rn, ..., ']' tokens when
parsing.

This allows us to do away with quite a bit of special C++ code to
handle monolithic "addressing modes" in the MC components. The more
incremental matching of the assembler operands also allows for better
diagnostics when LLVM is presented with invalid input.

Most of the complexity here is with the register-offset instructions,
which were extremely dodgy beforehand: even when the instruction used
wM, LLVM's model had xM as an operand. We papered over this
discrepancy before, but that approach doesn't work now so I split them
into separate X and W variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209425 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:56:09 +00:00
Daniel Sanders
e3ece90f24 [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6
Summary: Depends on D3787. Tablegen will raise an assertion without it.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3842

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:42:31 +00:00
Daniel Sanders
5f45ba140e [mips][mips64r6] Test that paired single instructions are invalid
Summary:
These emit the 'unknown instruction' instead of the correct error
because they have not been implemented in LLVM for any MIPS ISA.

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3841

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:37:38 +00:00
Daniel Sanders
c96096cc0f [mips][mips64r6] Add b[on]vc
Summary:
This required me to implement the disassembler for MIPS64r6 since the encodings
are ambiguous with other instructions. This in turn revealed a few
assembly/disassembly bugs which I have fixed.

* da[ht]i only take two operands according to the spec, not three.
* DecodeBranchTarget2[16] correctly handles wider immediates than simm16
  * Also made non-functional change to DecodeBranchTarget and
    DecodeBranchTargetMM to keep implementation style consistent between
    them.
* Difficult encodings are handled by a custom decode method on the most
  general encoding in the group. This method will convert the MCInst to a
  different opcode if necessary.

DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue
so disassembling some branch instructions emit incorrect output. This seems
to affect branches with delay slots on all MIPS ISA's. I've left this bug
for now and temporarily removed the check for the immediate on
bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests.

jialc and jic crash the disassembler for some reason. I've left these
instructions commented out for the moment.

Depends on D3760

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3761

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209415 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:23:21 +00:00
Saleem Abdulrasool
f4f930c795 MC: formalise some assertions into proper errors
Now that clang can be used as an assembler via the IAS, invalid assembler inputs
would cause the assertions to trigger.  Although we cannot recover from the
errors here, nor provide caret diagnostics, attempt to handle them slightly more
gracefully by reporting a fatal error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209387 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 02:18:10 +00:00
Saleem Abdulrasool
cba7ac7bda MC: correct IMAGE_REL_ARM_MOV32T relocation emission
This corrects the emission of IMAGE_REL_ARM_MOV32T relocations.  Previously, we
were avoiding the high portion of the relocation too early.  If there was a
section-relative relocation with an offset greater than 16-bits (65535), you
would end up truncating the high order bits of the offset.  Allow the current
relocation representation to flow through out the MC layer to the object writer.
Use the new ability to restrict recorded relocations to avoid emitting the
relocation into the final object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 23:17:56 +00:00
Eric Christopher
d1b5bdaebd Move MCOptions that aren't shared between programs into their specific
program and have them initialize the MCOptions struct explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209321 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 21:05:09 +00:00
Saleem Abdulrasool
5dd4b9f43b MC: loosen an overzealous assertion
Permit active macro expansions when terminating the assembler if there were
errors during the expansion.  This would only trigger on invalid input when
built with assertions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209309 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 17:53:18 +00:00
Daniel Sanders
820861536c [mips][mips64r6] Add bc[12](eq|ne)z
Summary: Depends on D3691

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209292 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 12:56:39 +00:00
Saleem Abdulrasool
8235ed1808 MC: mark COFF .drectve section as REMOVE
The .drectve section should be marked as IMAGE_SCN_LNK_REMOVE.  This matches what
the MSVC toolchain does and accurately reflects that this section should not be
emitted into the final binary.  This section is merely information for the
linker, comprising of additional linker directives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209273 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 05:15:01 +00:00
Eric Christopher
e648d75c60 This command line option is only used in one place. Move it there and
rename it to something more descriptive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209263 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-21 00:20:01 +00:00
Daniel Sanders
2bb463448b Temporarily revert: r209129 - [mips][mips64r6] Sorted *_ENC, *_DESC classes and tests
After discussion with Zoran, we have decided to temporarily revert this commit.
It's causing some difficult to resolve conflicts and we are under time pressure
to deliver an initial MIPS64r6 compiler.

We will re-apply an equivalent patch once the time pressure has passed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-20 14:46:24 +00:00
Bradley Smith
bdc6a7a506 [ARM64] Port basic-a64-diagnostics.s over to ARM64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209207 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-20 13:33:41 +00:00
Christian Pirker
6099306cec ARMEB: Additional test files for ARM fixups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209200 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-20 09:24:37 +00:00
Tim Northover
c9ff20e8c6 TableGen: convert InstAlias's Emit bit to an int.
When multiple aliases overlap, the correct string to print can often be
determined purely by considering the InstAlias declarations in some particular
order. This allows the user to specify that order manually when desired,
without resorting to hacking around with the default lexicographical order on
Record instantiation, which is error-prone and ugly.

I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4,
uxtw". That's only true if Rn is the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209199 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-20 09:17:16 +00:00
Jyotsna Verma
9bb7f7c390 reverting r209132
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209139 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-19 16:22:11 +00:00
Jyotsna Verma
3f19ce848d Hexagon: Add encoding bits to the mpy instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209132 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-19 15:32:07 +00:00
Zoran Jovanovic
78886bede2 [mips][mips64r6] Sorted *_ENC, *_DESC classes and tests
Differential Revision: http://reviews.llvm.org/D3808


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209129 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-19 14:57:46 +00:00
Reid Kleckner
1ce3088669 Add comdat key field to llvm.global_ctors and llvm.global_dtors
This allows us to put dynamic initializers for weak data into the same
comdat group as the data being initialized.  This is necessary for MSVC
ABI compatibility.  Once we have comdats for guard variables, we can use
the combination to help GlobalOpt fire more often for weak data with
guarded initialization on other platforms.

Reviewers: nlewycky

Differential Revision: http://reviews.llvm.org/D3499

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209015 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 20:39:27 +00:00
Zoran Jovanovic
fadf07b882 [mips][mips64r6] Add SELEQZ and SELNEZ instructions
Differential Revision: http://reviews.llvm.org/D3743


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208987 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 13:40:57 +00:00