Commit Graph

119430 Commits

Author SHA1 Message Date
Adam Nemet
31a4111f50 [LoopDist/LoopVer] Move LoopVersioning to a new module, NFC
Summary:
The class will obviously need improvement down the road.  For one, there
is no reason that addPHINodes would have to be exposed like that.  I
will make this and other improvements in follow-up patches.

The main goal is to be able to share this functionality.  The
LoopLoadElimination pass I am working on needs it too.  Later we can
move other clients as well (LV and Ashutosh's LICMVer).

Reviewers: hfinkel, ashutosh.nema

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241932 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:55:13 +00:00
Adam Nemet
8c3eef8b7c [LoopDist] Move loop-versioning helper functions to Cloning, NFC
Summary:
This makes them available to the LoopVersioning class as that is moved
to its own module in the next patch.

Reviewers: ashutosh.nema, hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10576

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241931 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:55:09 +00:00
Matthias Braun
74c23af006 ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code
This commit factors out common code from MergeBaseUpdateLoadStore() and
MergeBaseUpdateLSMultiple() and introduces a new function
MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a
strd/ldrd instruction into an strd/ldrd instruction with writeback where
possible.

Differential Revision: http://reviews.llvm.org/D10676

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241928 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:37:33 +00:00
Fiona Glaser
b0a2d8c5a5 ComputeKnownBits: be a bit smarter about ADDs
If our two inputs have known top-zero bit counts M and N, we trivially
know that the output cannot have any bits set in the top (min(M, N)-1)
bits, since nothing could carry past that point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241927 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:29:02 +00:00
Matthias Braun
02e89ace70 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2
Differential Revision: http://reviews.llvm.org/D10623

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241926 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:28:49 +00:00
JF Bastien
7bfd515593 WebAssembly: basic instructions todo, and basic register info.
Summary:
This code is based on AArch64 for modern backend good practice, and NVPTX for
virtual ISA concerns.

Reviewers: sunfish

Subscribers: aemerson, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11070

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241923 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:23:10 +00:00
Alex Lorenz
b83896903b MIR Serialization: Initial serialization of stack objects.
This commit implements the initial serialization of stack objects from the
MachineFrameInfo class. It can only serialize the ordinary stack objects
(including ordinary spill slots), but it doesn't serialize variable sized or
fixed stack objects yet.

The stack objects are serialized using a YAML sequence of YAML inline mappings.
Each mapping has the object's ID, type, size, offset and alignment. The stack
objects are a part of machine function's YAML mapping.

Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241922 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:13:57 +00:00
JF Bastien
99cb989593 Target RegisterInfo: devirtualize TargetFrameLowering
Summary:
The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can.

This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here.

Subscribers: sunfish, ted, llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241921 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:13:17 +00:00
Matthias Braun
892af54a91 ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.
This improves the logic in several ways and is a preparation for
followup patches:
- First perform an analysis and create a list of merge candidates, then
  transform. This simplifies the code in that you have don't have to
  care to much anymore that you may be holding iterators to
  MachineInstrs that get removed.
- Analyze/Transform basic blocks in reverse order. This allows to use
  LivePhysRegs to find free registers instead of the RegisterScavenger.
  The RegisterScavenger will become less precise in the future as it
  relies on the deprecated kill-flags.
- Return the newly created node in MergeOps so there's no need to look
  around in the schedule to find it.
- Rename some MBBI iterators to InsertBefore to make their role clear.
- General code cleanup.

Differential Revision: http://reviews.llvm.org/D10140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241920 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 18:08:49 +00:00
Eli Bendersky
98da4704dd Actually support volatile memcpys in NVPTX lowering
Differential Revision: http://reviews.llvm.org/D11091



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241914 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 15:40:33 +00:00
Nemanja Ivanovic
46c36cfa0f NFC. Added a blank line for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241913 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 14:25:17 +00:00
Benjamin Kramer
b0927bee8e [InstSimplify] Fold away ord/uno fcmps when nnan is present.
This is important to fold away the slow case of complex multiplies
emitted by clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241911 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 14:02:02 +00:00
James Molloy
ee0d992b07 Add support for fast-math flags to the FCmp instruction.
FCmp behaves a lot like a floating-point binary operator in many ways,
and can benefit from fast-math information. Flags such as nsz and nnan
can affect if this fcmp (in combination with a select) can be treated
as a fminnum/fmaxnum operation.

This adds backwards-compatible bitcode support, IR parsing and writing,
LangRef changes and IRBuilder changes. I'll need to audit InstSimplify
and InstCombine in a followup to find places where flags should be
copied.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241901 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 12:52:00 +00:00
Nemanja Ivanovic
e57b60a7f9 Add missing builtins to the PPC back end for ABI compliance (vol. 3)
This patch corresponds to review:
http://reviews.llvm.org/D10973

Back end portion of the third round of additions to altivec.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241900 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 12:38:08 +00:00
Alexey Bataev
f7dc9d0f5e Disable loop re-rotation for -Oz (patch by Andrey Turetsky)
After changes in rL231820 loop re-rotation is performed even in -Oz mode. Since loop rotation is disabled for -Oz, it seems loop re-rotation should be disabled too.
Differential Revision: http://reviews.llvm.org/D10961


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241897 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 10:37:09 +00:00
Pawel Bylica
8229e332bd [llvm-stress] Enhance scalar type selection from command line.
llvm-stress command line options like -generate-x86-fp80 has been replaced with one list-like option -types. E.g. llvm-stress -types=x86_fp80,i100,i256,half. Default types (i1, i8, i16, i32, i64, float, double) are always added at the beginning of that list.

Reviewers: hfinkel

Differential Revision: http://reviews.llvm.org/D10667

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241896 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 10:01:47 +00:00
NAKAMURA Takumi
89a6fba75e llvm/Object/ELF.h: Appease g++-4.7.2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241895 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 08:43:41 +00:00
David Majnemer
eddf9e2057 Revert the new EH instructions
This reverts commits r241888-r241891, I didn't mean to commit them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241893 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:15:17 +00:00
Daniel Jasper
d09a1e42ca Add missing 'const'. I don't think this is strictly required, but some
compiler configuration is giving me an error and it seems to be
recommended anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241892 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:09:20 +00:00
David Majnemer
ec83dbdc5e Tighten the verifier check for catchblock.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241891 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:01:07 +00:00
David Majnemer
2431442e67 Address Joseph's review comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241890 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:01:03 +00:00
David Majnemer
a5d05b7711 Address Reid's review feedback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241889 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:00:58 +00:00
David Majnemer
751c4be705 New EH representation for MSVC compatibility
Summary:
This introduces new instructions neccessary to implement MSVC-compatible
exception handling support.  Most of the middle-end and none of the
back-end haven't been audited or updated to take them into account.

Reviewers: rnk, JosephTremoulet, reames, nlewycky, rjmccall

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241888 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 07:00:44 +00:00
Bjorn Steinbrink
86ef198476 [InstCombine] Employ AliasAnalysis in FindAvailableLoadedValue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241887 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 06:55:49 +00:00
Bjorn Steinbrink
ad4d73941a [InstCombine] Properly combine metadata when replacing a load with another
Not doing this can lead to misoptimizations down the line, e.g. because
of range metadata on the replacing load excluding values that are valid
for the load that is being replaced.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241886 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 06:55:44 +00:00
Jingyue Wu
dde12814c7 [NVPTX] declare no vector registers
Summary:
Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll)
produces code with complex control flow which hurts later optimizations. Since
NVPTX doesn't have vector registers in LLVM's sense
(NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector
registers to effectively disable loop vectorization.

Reviewers: jholewinski

Subscribers: jingyue, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11089

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241884 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 04:31:56 +00:00
Reid Kleckner
b4eeb6bca5 [WinEH] Make sure LSDA tables are 4 byte aligned
Apparently this is important, otherwise _except_handler3 assumes that
the registration node is corrupted and ignores it.

Also fix a bug in WinEHPrepare where we would insert code after a
terminator instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241877 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 00:08:49 +00:00
Eli Bendersky
89a5e2532d Replace index-loops by range-based loops
NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241875 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 23:06:03 +00:00
Sanjay Patel
c68ccc1a70 [x86] enable machine combiner reassociations for scalar double-precision multiplies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241873 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:58:39 +00:00
Sanjay Patel
39f09b5150 [x86] enable machine combiner reassociations for scalar double-precision adds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241871 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:48:54 +00:00
Michael J. Spencer
478d483d7e Fix shadowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241870 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:42:21 +00:00
Michael J. Spencer
8109763d68 [Object][ELF] Support dumping hash-tables from files with no section table.
This time without breaking the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241869 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:32:24 +00:00
Alex Lorenz
ad6702ec23 MIR Serialization: Serialize the virtual register definitions.
The virtual registers are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the id of the virtual register and the register
class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:23:13 +00:00
Adam Nemet
81e7e2dfab [LAA] Fix grammar in debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241867 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:41 +00:00
Adam Nemet
1c25d370c1 [LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFC
Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT.
NeedRTCheck says whether we need checks and CanDoRT whether we can
generate the checks.  The idea is to encode three states with these:

     Need/Can:
(1) false/dont-care: no checks are needed
(2) true/false: we need checks but can't generate them
(3) true/true: we need checks and we can generate them

This is pretty unnecessary since the caller (analyzeLoop) is only
interested in whether we can generate the checks if we actually need
them (i.e. 1 or 3).

So this change cleans up to return just that (CanDoRTIfNeeded) and pulls
all the underlying logic into canCheckPtrAtRT.

By doing all this, we simplify analyzeLoop which is the complex function
in LAA.

There is further room for improvement here by using RtCheck.Need
directly rather than a new local variable NeedRTCheck but that's for a
later patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241866 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:17:38 +00:00
Reid Kleckner
5cf6c0b070 [WinEH] Give up on using CSRs across 32-bit invokes for now
The runtime does not restore CSRs when transferring control back to the
function handling the exception. According to the experts on IRC, LLVM's
register allocator has no way to model register clobbers that only
happen on one edge of the CFG. For now, don't worry about trying to use
the meager three CSRs available on 32-bit X86 and just say that such
invokes preserve nothing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241865 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 22:09:41 +00:00
Reid Kleckner
827f211e95 Expose sjlj preparation through opt for my own debugging purposes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241864 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:48:40 +00:00
Alex Lorenz
ccba68af82 MIR Parser: Report an error when parsing machine function with an empty body.
This commit adds a new error which is reported when the MIR Parser encounters
a machine function without any machine basic blocks. The machine verifier
expects that the machine functions have at least one MBB, and this error will
prevent machine functions without MBBs from reaching the machine verifier and
crashing with an assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241862 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:21:33 +00:00
Tom Stellard
847c023a2e AMDGPU: Add helper function for implicit parameter offsets.
Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:20:37 +00:00
JF Bastien
b5ebaf3ae5 Unbreak WebAssembly build
Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed.

Reviewers: sunfish, joker.eph, echristo

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11084

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241859 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:00:09 +00:00
JF Bastien
51e46420ea WebAssembly: add placeholder intrinsics header
Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11080

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241858 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:57:38 +00:00
Sanjoy Das
efec6ccae3 [ImplicitNullChecks] Fix a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:31 +00:00
Sanjoy Das
a5a3e2d58a [ImplicitNullChecks] Be smarter in picking the memory op.
Summary:
Before this change ImplicitNullChecks would only pick loads of the form:

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   movl 32(Reg), Reg2
```

but not (say)

```
   test Reg, Reg
   jz elsewhere
 fallthrough:
   inc Reg3
   movl 32(Reg), Reg2
```

This change teaches ImplicitNullChecks to look through "unrelated"
instructions like `inc Reg3` when searching for a load instruction
to convert to a trapping load.

Reviewers: atrick, JosephTremoulet, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:13:25 +00:00
Rafael Espindola
377796abdf Create BSD archives by default on OS X.
They should probably be created on anything that is not windows or linux, but I will
test on freebsd before changing that.

With this it is possible to bootstrap with llvm-ar instead of ar+ranlib on OS X.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241849 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 20:12:50 +00:00
Alex Lorenz
7c6ad33126 MIR Serialization: Serialize the simple MachineFrameInfo attributes.
This commit serializes the 13 scalar boolean and integer attributes from the
MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap,
HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack,
HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and
HasMustTailInVarArgFunc. These attributes are serialized as part
of the frameInfo YAML mapping, which itself is a part of the machine function's
YAML mapping.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241844 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:55:27 +00:00
Rafael Espindola
7255090cd3 llvm-ar: Pad the symbol table to 4 bytes.
It looks like ld64 requires it. With this we seem to be able to bootstrap using
llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 19:48:06 +00:00
Matt Arsenault
0685a5c5ed AMDGPU/R600: Return correct chain when lowering loads
The other LowerLOAD should be returning the correct chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:47:03 +00:00
Sanjoy Das
4db527032a [IndVars] Try to use existing values in RewriteLoopExitValues.
Summary:
In RewriteLoopExitValues, before expanding out an SCEV expression using
SCEVExpander, try to see if an existing LLVM IR expression already
computes the value we're interested in.  If so use that existing
expression.

Apart from reducing IndVars' reliance on the rest of the compilation
pipeline, this also prevents IndVars from concluding some expressions as
"high cost" when they're not.  For instance,
`InductiveRangeCheckElimination` often emits code of the following form:

```
len = umin(len_A, len_B)

loop:
  ...
  if (i++ < len)
    goto loop

outside_loop:
    use(i)
```

`SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`,
since it thinks the value of `i` on loop exit, `len`, is a high cost
expansion since it contains an `umax` in it.  With this change,
`IndVars` can see that it can re-use `len` instead of creating a new
expression to compute `umin(len_A, len_B)`.

I considered putting this cleverness in `SCEVExpander`, but I was
worried that it may then have a deterimental effect on other passes
that use it.  So I decided it was better to just do this in the one
place where it seems like an obviously good idea, with the intent of
generalizing later if needed.

Reviewers: atrick, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10782

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:46:12 +00:00
Simon Atanasyan
13c5e09c6e [llvm-readobj] Print MIPS PLT table
Now the -mips-plt-got prints both MIPS GOT and PLT tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241836 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:23:10 +00:00
Simon Atanasyan
ba8d948e93 [yaml2obj] Initialize sh_addralign field for the .symtab section
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241835 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:23:02 +00:00