Commit Graph

104 Commits

Author SHA1 Message Date
Eric Christopher
d568b3f552 Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 23:06:52 +00:00
David Greene
5e3cb47bea Use get(0 Instead of Create()
Respond to some feedback asking for a name change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134921 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 20:55:22 +00:00
David Greene
d4a9066c93 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 18:25:51 +00:00
Jim Grosbach
806fcc040e Don't require pseudo-instructions to carry encoding information.
For now this is distinct from isCodeGenOnly, as code-gen-only
instructions can (and often do) still have encoding information
associated with them. Once we've migrated all of them over to true
pseudo-instructions that are lowered to real instructions prior to
the printer/emitter, we can remove isCodeGenOnly and just use isPseudo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134539 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 21:33:38 +00:00
Owen Anderson
4cdcb4772d Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>".
Unfortunately, my only testcase for this is fragile, and the ARM AsmParser can't round trip the instruction in question.
<rdar://problem/9345702>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130410 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28 17:51:45 +00:00
Jim Grosbach
0ed92f2de3 Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-03 23:26:36 +00:00
Bob Wilson
9b8c3530cc Fix a comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27 23:08:52 +00:00
Jeffrey Yasskin
8e68c38735 Change all self assignments X=X to (void)X, so that we can turn on a
new gcc warning that complains on self-assignments and
self-initializations.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 00:58:24 +00:00
Bill Wendling
eac8f35da8 Move <map> include out of .h and into .cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121661 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 01:05:54 +00:00
Chris Lattner
67db883487 eliminate the Records global variable, patch by Garrison Venn!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-13 00:23:57 +00:00
Chris Lattner
8ae082bf19 pull the code to get the operand value out of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119130 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 07:09:28 +00:00
Chris Lattner
1620117f76 split the giant encoder loop into two new helper functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119129 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 06:59:17 +00:00
Chris Lattner
98e969ae20 reduce nesting and minor cleanups, no functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 06:42:13 +00:00
Chris Lattner
2ac190238e add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15 05:19:05 +00:00
Owen Anderson
336b8b4244 Add support for specifying a PostEncoderMethod, which can perform post-processing after the automated encoding of an instruction.
Not yet used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11 01:19:24 +00:00
Jim Grosbach
60aaa76196 Support generating an MC'ized CodeEmitter directly. Maintain a reference to the
Fixups list for the instruction so the operand encoders can add to it as
needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 23:38:14 +00:00
Jim Grosbach
ab3d00e535 Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
assumptions about stack layout. Specifically, LR must be saved next to FP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 17:35:25 +00:00
Jim Grosbach
cd5391965f Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 00:16:39 +00:00
Chris Lattner
c240bb0ede factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 04:03:32 +00:00
Jim Grosbach
5013f7469e Allow targets to optionally specify custom binary encoder functions for
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 22:21:57 +00:00
Jim Grosbach
a1e2194f03 The assert() should reference to machine instr operand number, too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:41:31 +00:00
Jim Grosbach
1a7233f9d0 Make sure to use the machine instruction operand number. It doesn't always
map one-to-one with the CodeGenInstruction operand number.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116238 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 21:31:22 +00:00
Jim Grosbach
01855071e2 When figuring out which operands match which encoding fields in an instruction,
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 18:25:51 +00:00
Jim Grosbach
bade37bb8b Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:21:28 +00:00
Jim Grosbach
8b892ae3d6 trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115923 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 16:56:28 +00:00
Jakob Stoklund Olesen
65766ce7df Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02 21:44:22 +00:00
Evan Cheng
b55c8bed9d Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:28:44 +00:00
Chris Lattner
75361b69f3 rename llvm::llvm_report_error -> llvm::report_fatal_error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:58:41 +00:00
Chris Lattner
f65027842e change Target.getInstructionsByEnumValue to return a reference
to a vector that CGT stores instead of synthesizing it on every 
call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:34:35 +00:00
Chris Lattner
f30187a363 look up instructions by record, not by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:07:20 +00:00
Chris Lattner
518bb53485 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-09 19:54:29 +00:00
Dale Johannesen
243a32f96b Remove DEBUG_DECLARE, looks like we don't need it.
Also, DEBUG_VALUE has side effects.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-15 01:50:44 +00:00
Dale Johannesen
d2035203a0 Add DEBUG_DECLARE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-09 01:24:25 +00:00
Dale Johannesen
87563b3937 Add DEBUG_VALUE. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-08 23:51:25 +00:00
Dan Gohman
9b03da6824 Revert 90628, which was incorrect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91448 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 20:21:44 +00:00
Dan Gohman
7004b9cf33 Minor code simplification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90628 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-05 00:05:43 +00:00
Jakob Stoklund Olesen
26207e5bf1 Introduce the TargetInstrInfo::KILL machine instruction and get rid of the
unused DECLARE instruction.

KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-28 20:32:26 +00:00
Torok Edwin
804e0fea40 Convert more abort() calls to llvm_report_error().
Also remove trailing semicolon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75027 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08 19:04:27 +00:00
Daniel Dunbar
1a55180238 Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

 - No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03 00:10:29 +00:00
Dan Gohman
88c7af096b Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalize
it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 21:06:25 +00:00
Dan Gohman
f8c7394781 Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13 15:38:05 +00:00
Chris Lattner
1cfa0776c3 Fix shift overflow bug that would occur when a field was a full 32-bits
in tblgen.  This is PR2827, thanks to Waldemar Knorr for tracking this
down.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57124 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-05 18:31:58 +00:00
Evan Cheng
bc95b23156 Add instruction names as comments to InstBits entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56275 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-17 06:29:52 +00:00
Evan Cheng
e3e3626338 Eliminate a compile time warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55878 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-07 09:00:57 +00:00
Evan Cheng
acff339e39 Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-02 06:51:36 +00:00
Dan Gohman
4406604047 Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01 00:05:16 +00:00
Christopher Lamb
c929823525 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16 03:12:01 +00:00
Evan Cheng
da47e6e0d0 Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15 00:03:38 +00:00
Evan Cheng
a844bdeab3 SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02 04:07:54 +00:00
Chris Lattner
3060910e29 remove attributions from utils.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:37:13 +00:00