llvm-6502

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Commit Graph

Author	SHA1	Message	Date
Nadav Rotem	3e40d927a7	ARM Cost Model: Modify the target independent cost model to ask the target if it supports the different CAST types. We didn't do this on X86 because of the different register sizes and types, but on ARM this makes sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172245 91177308-0d34-0410-b5e6-96231b3b80d8	2013-01-11 19:54:13 +00:00
Nadav Rotem	14925e6b88	ARM Cost model: Use the size of vector registers and widest vectorizable instruction to determine the max vectorization factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172010 91177308-0d34-0410-b5e6-96231b3b80d8	2013-01-09 22:29:00 +00:00

Author

SHA1

Message

Date

Nadav Rotem

3e40d927a7

ARM Cost Model: Modify the target independent cost model to ask

the target if it supports the different CAST types. We didn't do this
on X86 because of the different register sizes and types, but on ARM
this makes sense.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172245 91177308-0d34-0410-b5e6-96231b3b80d8

2013-01-11 19:54:13 +00:00

Nadav Rotem

14925e6b88

ARM Cost model: Use the size of vector registers and widest vectorizable instruction to determine the max vectorization factor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172010 91177308-0d34-0410-b5e6-96231b3b80d8

2013-01-09 22:29:00 +00:00

2 Commits