6cadd406cc
R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 20:12:39 +00:00
7e06370873
R600/SI: Custom lower i1 stores
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These are sometimes created by the shrink to boolean optimization in the
globalopt pass.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203280 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-07 20:12:33 +00:00
161e3a80b2
R600: Fix extloads from i8 / i16 to i64.
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This appears to only be working for global loads. Private
and local break for other reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:34:12 +00:00
b4cd160bb9
R600/SI: Expand selects on vectors.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203134 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:34:03 +00:00
0c5c3b93d8
Fix missing C++ mode comment
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203133 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 17:33:58 +00:00
67f6bf70d2
[Layering] Move InstVisitor.h into the IR library as it is pretty
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obviously coupled to the IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203064 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 03:23:41 +00:00
af0cc459bf
Fix typo
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203013 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-05 21:47:22 +00:00
7225e27b4c
[Modules] Move ValueMap to the IR library. While this class does not
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directly care about the Value class (it is templated so that the key can
be any arbitrary Value subclass), it is in fact concretely tied to the
Value class through the ValueHandle's CallbackVH interface which relies
on the key type being some Value subclass to establish the value handle
chain.
Ironically, the unittest is already in the right library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202824 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-04 11:26:31 +00:00
d628f19f5d
[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.
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Remove the old functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 12:27:27 +00:00
629b96cb4f
Switch all uses of LLVM_OVERRIDE to just use 'override' directly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202621 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 09:09:27 +00:00
4eb03f049e
Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202618 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-02 08:08:51 +00:00
34faf78241
R600: Verify all instructions in the AsmPrinter on debug builds
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Make a call to R600's implementation of verifyInstruction() to
check that instructions are only using legal operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202544 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 21:36:41 +00:00
9f0d68f522
R600/SI: Expand all v16[if]32 operations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202543 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-28 21:36:37 +00:00
b9e06b97ce
Remove MCPureStreamer.
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We moved MCJIT to use native object formats a long time ago and R600
now uses ELF, so it was dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202408 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 16:17:34 +00:00
644aecfc97
R600/SI: Optimize SI_KILL for constant operands
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If the SI_KILL operand is constant, we can either clear the exec mask if
the operand is negative, or do nothing otherwise.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202337 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 01:47:09 +00:00
a5fbf24716
R600/SI: Allow SI_KILL for geometry shaders
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Reviewed-by: Tom Stellard <thomas.stellard@amd.com >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-27 01:47:02 +00:00
3f19b69b01
R600: Remove unnecessary build_vector pattern.
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It is already fully handled in AMDGPUISelDAGToDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202312 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-26 23:00:58 +00:00
431e9f0310
R600: Don't unconditionally unroll loops with private memory accesses
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This causes the size of the scrypt kernel to explode and eats all the
memory on some systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202195 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:21 +00:00
d8c31046a9
R600/SI: Custom select 64-bit ADD
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-25 21:36:18 +00:00
2e4ab2aa8a
Fix unused variable
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202080 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:16:50 +00:00
bc247e4afd
R600/SI - Add new CI arithmetic instructions.
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Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:28 +00:00
3f9f4bc0af
R600: Make check clearer.
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The check is clearer as southern islands or later,
rather than checking for later than northern islands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202076 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:23 +00:00
e87a1a9e2c
Fix DOT4 missing from getTargetOpcodeName
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202075 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-24 21:01:21 +00:00
0f2e653317
R600/SI: Expand all v8[if]32 operations
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201371 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:15 +00:00
9757ba1206
R600/SI: Add a pattern for i32 anyext
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201370 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:13 +00:00
130f271259
R600/SI: Completely Disable TypeRewriter on compute
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201369 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:12 +00:00
1a52c2b25a
R600/SI: Split global vector loads with more than 4 elements
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201368 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-13 23:34:10 +00:00
eee40f92a9
R600: Always implement both versions of isTruncateFree and add a sanity check.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201222 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-12 10:17:54 +00:00
69bc4ddf10
R600/SI: Fix assertion on infinite loops.
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This isn't the most useful case to fix in the real world,
but bugpoint runs into this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201177 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-11 21:12:38 +00:00
700bba297b
R600: Implement isTruncateFree
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Truncation is just accessing a subregister for any multiple of
the register size, so it's free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201107 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 19:57:42 +00:00
42faffddb9
R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used
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DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0. When M0 is uninitialized,
then we experience undefined behavior.
This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 16:58:30 +00:00
835f1c01bf
R600/SI: Only use S_WQM_B64 in pixel shaders
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This doesn't change any functionality, since we only have two shader
types (compute and pixel) that use local memory. We're just changing
the logic to match the documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201096 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-10 16:58:27 +00:00
226bd876c6
R600/SI: Add a MUBUF store pattern for Reg+Imm offsets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200935 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:41 +00:00
603cd56372
R600/SI: Add a MUBUF store pattern for Imm offsets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200934 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:39 +00:00
becac0f183
R600/SI: Add a MUBUF load pattern for Reg+Imm offsets
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200933 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:38 +00:00
22274378d5
R600/SI: Use immediates offsets for SMRD instructions whenever possible
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There was a problem with the old pattern, so we were copying some
larger immediates into registers when we could have been encoding
them in the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200932 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-06 18:36:34 +00:00
bb7bf85f3c
Add address space argument to allowsUnalignedMemoryAccess.
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On R600, some address spaces have more strict alignment
requirements than others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 23:15:53 +00:00
cf4061a601
R600/SI: Add pattern for zero-extending i1 to i32
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Fixes opencl-example if_* tests with radeonsi.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469
Reviewed-by: Tom Stellard <thomas.stellard@amd.com >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200830 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 09:48:05 +00:00
483727da48
cleanup: scc_iterator consumers should use isAtEnd
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No functional change. Updated loops from:
for (I = scc_begin(), E = scc_end(); I != E; ++I)
to:
for (I = scc_begin(); !I.isAtEnd(); ++I)
for teh win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200789 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 19:19:07 +00:00
5e47632b8f
Every target uses .align. Simplify.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200782 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 18:39:51 +00:00
7d9ed1cac5
R600/SI: Expand i1 BR_CC
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This fixes a crashes in the OpenCV test suite and also the scrypt
kernel in bfgminer.
I was unable to come up with a reduced test case for this.
https://bugs.freedesktop.org/show_bug.cgi?id=72785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200776 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:43 +00:00
0c7a6b6477
R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopies
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There is no lit test for this, because it would be too big and
complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200775 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:42 +00:00
83918a2ad2
R600/SI: Custom lower i64 ISD::SELECT
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200774 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:40 +00:00
4ee42eaec9
R600: Enable vector fpow.
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The OpenCL specs say: "The vector versions of the math functions operate
component-wise. The description is per-component."
Patch by: Jan Vesely
Reviewed-by: Tom Stellard <thomas.stellard@amd.com >
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200773 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 17:18:37 +00:00
de2e0bc366
R600/SI: Fix fneg for 0.0
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V_ADD_F32 with source modifier does not produce -0.0 for this. Just
manipulate the sign bit directly instead.
Also add a pattern for (fneg (fabs ...)).
Fixes a bunch of bit encoding piglit tests with radeonsi.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com >
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200743 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-04 07:12:38 +00:00
2a3e343d86
Add DEBUG_TYPE to SIAnnotateControlFlow
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200720 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-03 22:58:05 +00:00
b2abb9752e
R600/SI: Fix insertelement with dynamic indices.
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This didn't work for any integer vectors, and didn't
work with some sizes of float vectors. This should now
work with all sizes of float and i32 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200619 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-02 00:05:35 +00:00
9d96045528
Remove the last hasRawTextSupport call from R600.
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There is nothing wrong with printing the disassembly section when printing
text. An hypothetical assembler would then produce a .o just like our
direct object emission produces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200583 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 22:14:06 +00:00
b8f1606076
Replace another use with hasRawTextSupport+EmitRawText with emitRawComment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200582 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 22:08:19 +00:00
f7af9eac1b
Use emitRawComment to avoid a call to hasRawTextSupport.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200581 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-31 21:54:49 +00:00