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20887 Commits

Author SHA1 Message Date
Jim Grosbach
c7448f8d47 ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns. 
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:55:21 +00:00
Jim Grosbach
8c748113eb Remove some bogus comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:45:01 +00:00
Jim Grosbach
1aa149f5ac ARM pre-UAL aliases. fcmp[sd]. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 19:20:45 +00:00
Rafael Espindola
f51e95a9f2 Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for reporting 
it. It does need some some tests...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147154 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 18:38:06 +00:00
Jim Grosbach
8d9550bde9 ARM assembler should accept shift-by-zero for any shifted-immediate operand. 
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 18:04:04 +00:00
Jim Grosbach
de626ad872 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:37:00 +00:00
Jim Grosbach
18c8d12dea Tidy up. Trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:17:10 +00:00
Jim Grosbach
f1a88fc474 Nuke invalid comment from copy/paste. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 17:04:50 +00:00
Rafael Espindola
090445967f Move the Mips only bits of the ELF writer to lib/Target/Mips. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147133 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 03:03:17 +00:00
Rafael Espindola
6db2d92603 Make the virtual methods in ARMELFObjectWriter public. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147132 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 02:58:12 +00:00
Rafael Espindola
4982159b88 Move the MBlaze ELF writer bits to lib/Target/MBlaze. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147129 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 02:28:24 +00:00
Rafael Espindola
dcc557f146 Fix cmake. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147126 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 02:06:17 +00:00
Rafael Espindola
f3a86fb03d Move PPC bits to lib/Target/PowerPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147124 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:57:09 +00:00
Rafael Espindola
81fafde8a6 Hopefully fix the cmake build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:11:01 +00:00
Rafael Espindola
7609785d2b Fix name in comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:06:53 +00:00
Akira Hatanaka
bc24985c5f Local dynamic TLS model for direct object output. Create the correct TLS MIPS 
ELF relocations.

Patch by Jack Carter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147118 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:05:17 +00:00
Richard Smith
74cab51aa5 Unbreak cmake build after r147115. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147117 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 01:03:35 +00:00
Rafael Espindola
69bbda0391 Move the ARM specific parts of the ELF writer to Target/ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-22 00:37:50 +00:00
Jim Grosbach
f7c66fa0de ARM NEON mnemonic aliase for vrecpeq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:52:37 +00:00
Jim Grosbach
af33a0cfe0 ARM VFP optional data type on VMOV GPR<-->SPR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:24:15 +00:00
Jim Grosbach
5f669fa8ba ARM NEON optional data type on VSWP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:09:28 +00:00
Jim Grosbach
4553fa3128 ARM NEON mnemonic aliases for vzipq and vswpq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:04:33 +00:00
Jim Grosbach
de4d83943a ARM asm parser should be more lenient w/ .thumb_func directive. 
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 22:30:16 +00:00
Jim Grosbach
520dc78d92 Thumb2 assembly parsing of 'mov rd, rn, rrx'. 
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 21:04:19 +00:00
Chad Rosier
5c0d761d63 Fix 80-column violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:59:09 +00:00
Jim Grosbach
2cc5cda464 Thumb2 assembly parsing of 'mov(register shifted register)' aliases. 
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 20:54:00 +00:00
Jakob Stoklund Olesen
a2a98fd0dd Move common code into an MRI function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:50:05 +00:00
Jim Grosbach
e6949b1399 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:40:55 +00:00
Chad Rosier
649326ab15 No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't 
necessary.  Please chime in if I'm mistaken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:14:52 +00:00
Chad Rosier
8d0447c506 Fix a couple of copy-n-paste bugs. Noticed by George Russell! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 18:56:22 +00:00
Rafael Espindola
edae8e1e4d Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147060 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:30:17 +00:00
Rafael Espindola
dc9a8a378d Reduce the exposure of Triple::OSType in the ELF object writer. This will 
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 17:00:36 +00:00
Craig Topper
224c1b275d Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147046 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 08:06:52 +00:00
Craig Topper
e1a18a66df Fix typo in a couple comments 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 06:30:53 +00:00
Evan Cheng
1e33e8b715 Fix a couple of copy-n-paste bugs. Noticed by George Russell. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 03:04:10 +00:00
Jim Grosbach
c931325d99 ARM assembly parsing allows constant expressions for lane indices. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 01:19:23 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Akira Hatanaka
c7541c49a9 Fix bug in zero-store peephole pattern reported in pr11615. 
The patch and test case were originally written by Mans Rullgard.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:31:10 +00:00
Akira Hatanaka
c79507a4dd Expand 64-bit CTLZ nodes if target architecture does not support it. Add test 
case for DCLO and DCLZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:20:27 +00:00
Akira Hatanaka
7f162743fc Expand 64-bit CTPOP and CTTZ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
9aed504c82 Expand 64-bit atomic load and store. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
c0ea04389c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:56:43 +00:00
Akira Hatanaka
4d2b0f3ce7 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
e1bcd6b5c6 64-bit uint-fp conversion nodes are expanded. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
9388383b34 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
056a1bc40f Set the correct stack pointer register that should be saved or restored. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:28:36 +00:00
Jim Grosbach
aee718beac ARM .req register name aliases are case insensitive, just like regnames. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:11:00 +00:00
Akira Hatanaka
2fd0475cdb Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
49d534bb3d Fix indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
8dc684d2a2 64-bit data directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 22:52:19 +00:00