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c884db47f1
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2568 Commits

Author SHA1 Message Date
Jeff Cohen
c884db47f1 Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28044 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-02 01:16:28 +00:00
Chris Lattner
229924a79f Fix a latent bug that my spiller patch last week exposed: we were leaving 
instructions in the virtregfolded map that were deleted.  Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map.  The solution is to remove entries
from the map when we delete the instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28041 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 22:03:24 +00:00
Chris Lattner
8a18c13fa5 When promoting a load to a reg-reg copy, where the load was a previous 
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28040 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 21:17:10 +00:00
Chris Lattner
35f2705e3d Remove previous patch, which wasn't quite right. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28039 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 21:16:03 +00:00
Evan Cheng
22608c2d1f Dis-favor stores more 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28035 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 09:20:44 +00:00
Evan Cheng
f229a5d4be Bottom up register-pressure reduction scheduler now pushes store operations 
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28033 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 09:14:40 +00:00
Evan Cheng
3766d66b91 Didn't mean ScheduleDAGList.cpp to make the last checkin. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28030 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 08:56:34 +00:00
Evan Cheng
10dbd3ead8 Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28029 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 08:54:57 +00:00
Chris Lattner
c80c43eee0 Format #APP lines a bit nicer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28026 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-01 04:11:03 +00:00
Evan Cheng
200370fb56 Local spiller kills a store if the folded restore is turned into a copy. 
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28024 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-30 08:41:47 +00:00
Chris Lattner
25c344a758 Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c 
with some changes I have to the new CFE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 23:33:20 +00:00
Evan Cheng
55d0fa1bfa Remove the temporary option: -no-isel-fold-inflight 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28012 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 18:54:11 +00:00
Evan Cheng
020c41f21e TargetLowering::LowerArguments should return a VBIT_CONVERT of 
FORMAL_ARGUMENTS SDOperand in the return result vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 05:25:15 +00:00
Chris Lattner
ba1fc3daf7 Mapping of physregs can make it so that the designated and input physregs are 
the same.  In this case, don't emit a noop copy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28008 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 04:43:18 +00:00
Evan Cheng
552c4a8494 Added a temporary option -no-isel-fold-inflight to control whether a "inflight" 
node can be folded.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28003 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 02:09:19 +00:00
Chris Lattner
addc55af6c When we have a two-address instruction where the input cannot be clobbered 
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy.  This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write.  As one example, this change does:

        pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
        xorps %XMM2, %XMM5
        cmpltps %XMM1, %XMM0
-       movaps XMMWORD PTR [%ESP + 52], %XMM0
-       movapd %XMM6, XMMWORD PTR [%ESP + 52]
+       movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
        movapd XMMWORD PTR [%ESP + 52], %XMM6
        movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
        cmpltps %XMM3, %XMM0
-       movaps XMMWORD PTR [%ESP + 20], %XMM0
-       movapd %XMM7, XMMWORD PTR [%ESP + 20]
+       movaps %XMM7, %XMM0
        cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
        movapd XMMWORD PTR [%ESP + 20], %XMM7
        cmpltps %XMM4, %XMM0

... which is far better than a store followed by a load!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28001 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-28 01:46:50 +00:00
Evan Cheng
f7179bb56e Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses 
(VAND, VADD, etc.). Legalizer will assert otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27991 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-27 08:29:42 +00:00
Chris Lattner
a83385fb7b Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and 
PR748.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27987 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-27 05:01:07 +00:00
Evan Cheng
3b0d286d00 Don't forget return void. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27974 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-25 23:03:35 +00:00
Nate Begeman
9453eea49b Fix the updating of the machine CFG when a PHI node was in a successor of 
the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27952 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-23 06:26:20 +00:00
Nate Begeman
3700a4d3a2 Code cleanup associated with jump tables, thanks to Chris for noticing 
these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27950 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 23:52:35 +00:00
Nate Begeman
05f9466cf0 Turn of jump tables for a bit, there are still some issues to work out with 
updating the machine CFG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27949 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 23:51:56 +00:00
Nate Begeman
37efe67645 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-22 18:53:45 +00:00
Chris Lattner
4a1cd9c61e The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap 
miscompares).  Switch RISC targets to use the list-td scheduler, which isn't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27933 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-21 17:16:16 +00:00
Chris Lattner
ef027f940c Fix a couple more memory issues 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27930 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-21 15:32:26 +00:00
Chris Lattner
fedced7bc3 Fix a really subtle and obnoxious memory bug that caused issues with an 
llvm-gcc4 boostrap.  Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27922 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 23:55:59 +00:00
Chris Lattner
1b87c42c82 This field no longer exists 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27899 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 18:32:41 +00:00
Chris Lattner
02e5f8dcda Remove some of the obvious V9-specific cruft 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27893 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 18:08:53 +00:00
Evan Cheng
44f1f09b4e Turn a VAND into a VECTOR_SHUFFLE is applicable. 
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27874 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 08:56:16 +00:00
Chris Lattner
62b5772959 Implement folding of a bunch of binops with undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27863 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-20 05:39:12 +00:00
Chris Lattner
89a1b380a4 Simplify some code 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27846 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-19 23:17:50 +00:00
Chris Lattner
80edfb3af5 Fix handling of calls in functions that use vectors. This fixes a crash on 
the code in GCC PR26546.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27780 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 22:10:08 +00:00
Chris Lattner
48d7c069c7 Add a MachineInstr::eraseFromParent convenience method. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27775 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 21:35:41 +00:00
Chris Lattner
8d5a894501 Codegen insertelement with constant insertion points as scalar_to_vector 
and a shuffle.  For this:

void %test2(<4 x float>* %F, float %f) {
        %tmp = load <4 x float>* %F             ; <<4 x float>> [#uses=2]
        %tmp3 = add <4 x float> %tmp, %tmp              ; <<4 x float>> [#uses=1]
        %tmp2 = insertelement <4 x float> %tmp3, float %f, uint 2               ; <<4 x float>> [#uses=2]
        %tmp6 = add <4 x float> %tmp2, %tmp2            ; <<4 x float>> [#uses=1]
        store <4 x float> %tmp6, <4 x float>* %F
        ret void
}

we now get this on X86 (which will get better):

_test2:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, %xmm1
        shufps $3, %xmm1, %xmm1
        movaps %xmm0, %xmm2
        shufps $1, %xmm2, %xmm2
        unpcklps %xmm1, %xmm2
        movss 8(%esp), %xmm1
        unpcklps %xmm1, %xmm0
        unpcklps %xmm2, %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        ret

instead of:

_test2:
        subl $28, %esp
        movl 32(%esp), %eax
        movaps (%eax), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%esp)
        movss 36(%esp), %xmm0
        movss %xmm0, 8(%esp)
        movaps (%esp), %xmm0
        addps %xmm0, %xmm0
        movaps %xmm0, (%eax)
        addl $28, %esp
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27765 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-17 19:21:01 +00:00
Chris Lattner
2efce0a589 Add support for promoting stores from one legal type to another, allowing us 
to write one pattern for vector stores instead of 4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27730 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-16 01:36:45 +00:00
Chris Lattner
547a16f273 Make these predicates return true for bit_convert(buildvector)'s as well as 
buildvectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27723 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-15 23:38:00 +00:00
Chris Lattner
3824e50b1e Make this assertion better 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27695 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-14 06:08:35 +00:00
Reid Spencer
60d07eeffe Expand some code with temporary variables to rid ourselves of the warning 
about "dereferencing type-punned pointer will break strict-aliasing rules"


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27671 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-13 18:29:58 +00:00
Evan Cheng
cc9876124e Promote vector AND, OR, and XOR 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27632 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 21:20:24 +00:00
Evan Cheng
41f6cbbeb2 Vector type promotion for ISD::LOAD and ISD::SELECT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27606 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 16:33:18 +00:00
Chris Lattner
fdfded5588 Implement support for the formal_arguments node. To get this, targets shouldcustom legalize it and remove their XXXTargetLowering::LowerArguments overload 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27604 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 16:20:43 +00:00
Chris Lattner
9d956250f5 Don't memoize vloads in the load map! Don't memoize them anywhere here, let 
getNode do it.  This fixes CodeGen/Generic/2006-04-11-vecload.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27602 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-12 03:25:41 +00:00
Evan Cheng
98f8aeb45f Only get Tmp2 for cases where number of operands is > 1. Fixed return void. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27586 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-11 06:33:39 +00:00
Chris Lattner
b49e52c7e2 add some todos 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27580 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-11 02:00:08 +00:00
Chris Lattner
f87324e44d Add basic support for legalizing returns of vectors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27578 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-11 01:31:51 +00:00
Jim Laskey
1069fbdd2f Use existing information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27574 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-10 23:09:19 +00:00
Evan Cheng
db3c626eb9 Missing break 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27559 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-10 18:54:36 +00:00
Chris Lattner
b22e35a3c3 Add code generator support for VSELECT 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27542 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-08 22:22:57 +00:00
Chris Lattner
17614ea63d Canonicalize vvector_shuffle(x,x) -> vvector_shuffle(x,undef) to enable patterns 
to match again :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27533 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-08 05:34:25 +00:00
Chris Lattner
3e104b1116 Codegen shufflevector as VVECTOR_SHUFFLE 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27529 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-08 04:15:24 +00:00