Commit Graph

124 Commits

Author SHA1 Message Date
Will Newton
87a2f3751c Update AArch64 ELF relocations to ABI 1.0
This mostly entails adding relocations, however there are a couple of
changes to existing relocations:

1. R_AARCH64_NONE is defined to be zero rather than 256

R_AARCH64_NONE has been defined to be zero for a long time elsewhere
e.g. binutils and glibc since the submission of the AArch64 port in
2012 so this is required for compatibility.

2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21

I don't think there is any way for relocation names to leak out of LLVM
so this should not break anything.

Tested with check-all with no regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 10:49:18 +00:00
Chad Rosier
fa16693864 [AArch64] Add support for the .inst directive.
This has been implement using the MCTargetStreamer interface as is done in the
ARM, Mips and PPC backends.

Phabricator: http://reviews.llvm.org/D5891
PR20964

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220422 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-22 20:35:57 +00:00
Tom Coxon
01649dea92 [AArch64] Allow access to all system registers with MRS/MSR instructions.
The A64 instruction set includes a generic register syntax for accessing
implementation-defined system registers. The syntax for these registers is:
    S<op0>_<op1>_<CRn>_<CRm>_<op2>

The encoding space permitted for implementation-defined system registers
is:
    op0 op1  CRn   CRm   op2
    11  xxx  1x11  xxxx  xxx

The full encoding space can now be accessed:
    op0 op1  CRn   CRm   op2
    xx  xxx  xxxx  xxxx  xxx

This is useful to anyone needing to write assembly code supporting new
system registers before the assembler has learned the official names for
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-01 10:13:59 +00:00
Jim Grosbach
bd847644b3 AArch64: allow constant expressions for shifted reg literals
e.g., add w1, w2, w3, lsl #(2 - 1)

This sort of thing comes up in pre-processed assembly playing macro games.
Still validate that it's an assembly time constant. The early exit error check
was just a bit overzealous and disallowed a left paren.

rdar://18430542

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-23 22:16:02 +00:00
Saleem Abdulrasool
0086358325 MC: AsmLexer: handle multi-character CommentStrings correctly
As X86MCAsmInfoDarwin uses '##' as CommentString although a single '#' starts a
comment a workaround for this special case is added.

Fixes divisions in constant expressions for the AArch64 assembler and other
targets which use '//' as CommentString.

Patch by Janne Grunau!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-14 02:51:43 +00:00
Chad Rosier
4e78deb350 Add test case omitted in r214974.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214975 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-06 16:06:41 +00:00
Tim Northover
8b6257629a AArch64: remove "arm64_be" support in favour of "aarch64_be".
There really is no arm64_be: it was a useful fiction to test big-endian support
while both backends existed in parallel, but now the only platform that uses
the name (iOS) doesn't have a big-endian variant, let alone one called
"arm64_be".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213748 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 12:58:11 +00:00
David Peixotto
12f33da20b MC: support different sized constants in constant pools
On AArch64 the pseudo instruction ldr <reg>, =... supports both
32-bit and 64-bit constants. Add support for 64 bit constants for
the pools to support the pseudo instruction fully.

Changes the AArch64 ldr-pseudo tests to use 32-bit registers and
adds tests with 64-bit registers.

Patch by Janne Grunau!

Differential Revision: http://reviews.llvm.org/D4279



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213387 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 16:05:14 +00:00
Tilmann Scheller
2dade438d7 [AArch64] Add negative tests for the SIMD & FP LDP instructions.
LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213074 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 16:33:24 +00:00
Arnaud A. de Grandmaison
a9af0558b2 [AArch64] Add logical alias instructions to MC AsmParser
This patch teaches the AsmParser to accept some logical+immediate
instructions and convert them as shown:

  bic  Rd, Rn, #imm  ->  and Rd, Rn, #~imm
  bics Rd, Rn, #imm  ->  ands Rd, Rn, #~imm
  orn  Rd, Rn, #imm  ->  orr Rd, Rn, #~imm
  eon  Rd, Rn, #imm  ->  eor Rd, Rn, #~imm

Those instructions are an alternate syntax available to assembly coders,
and are needed in order to support code already compiling with some other
assemblers. For example, the bic construct is used by the linux kernel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-10 15:12:26 +00:00
Arnaud A. de Grandmaison
60d8767211 Truncate the immediate in logical operation to the register width
And continue to produce an error if the 32 most significant bits are not all ones or zeros.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212520 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-08 09:53:04 +00:00
Tim Northover
5b003bb869 llvm-readobj: fix MachO relocatoin printing a bit.
There were two issues here:
1. At the very least, scattered relocations cannot use the same code to
   determine the corresponding symbol being referred to. For some reason we
   pretend there is no symbol, even when one actually exists in the symtab, so to
   match this behaviour getRelocationSymbol should simply return symbols_end for
   scattered relocations.
2. Printing "-" when we can't get a symbol (including the scattered case, but
   not exclusively), isn't that helpful. In both cases there *is* interesting
   information in that field, so we should print it. As hex will do.

Small part of rdar://problem/17553104

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212332 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-04 10:57:56 +00:00
Saleem Abdulrasool
8f9108459e aarch64: support target-specific .req assembler directive
Based on the support for .req on ARM. The aarch64 variant has to keep track if
the alias register was a vector register (v0-31) or a general purpose or
VFP/Advanced SIMD ([bhsdq]0-31) register.

Patch by Janne Grunau!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212161 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-02 04:50:23 +00:00
NAKAMURA Takumi
e572ec68d2 ldr-pseudo-obj-errors.s: Fix silly copypasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211642 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 23:18:07 +00:00
NAKAMURA Takumi
d14e98ad5b llvm/test/MC/AArch64/ldr-pseudo-obj-errors.s: Add -triple=aarch64-linux. AArch64 is unaware of PECOFF for now.
FIXME: This should pass for also targeting aarch64-darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211640 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 23:11:42 +00:00
Weiming Zhao
1357f0e1a7 Fix test case in r211605/r211533
The test case in
"Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64" should
only work with Linux.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 17:05:43 +00:00
Weiming Zhao
c33b4883b3 Resubmit commit r211533
"Fix PR20056: Implement pseudo LDR <reg>, =<literal/label> for AArch64"
Missed files are added in this commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211605 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 16:21:38 +00:00
Artyom Skrobov
45a31492d5 Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-10 13:11:35 +00:00
Alp Toker
8aeca44558 Reduce verbiage of lit.local.cfg files
We can just split targets_to_build in one place and make it immutable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210496 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 22:42:55 +00:00
Artyom Skrobov
a8d18fe946 [AArch64] Missing aliases for CMP/CMN [W]SP with no shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-09 11:10:14 +00:00
Alp Toker
3c9b41b949 Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210401 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-07 21:23:09 +00:00
Artyom Skrobov
684122e84e Add missing check when MatchInstructionImpl() reports failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209802 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-29 11:26:15 +00:00
Tim Northover
29f94c7201 AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:50:23 +00:00
Tim Northover
9105f66d6f AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-24 12:42:26 +00:00
Tim Northover
e072ed71c8 ARM64: separate load/store operands to simplify assembler
This changes ARM64 to use separate operands for each component of an
address, and look for separate '[', '$Rn, ..., ']' tokens when
parsing.

This allows us to do away with quite a bit of special C++ code to
handle monolithic "addressing modes" in the MC components. The more
incremental matching of the assembler operands also allows for better
diagnostics when LLVM is presented with invalid input.

Most of the complexity here is with the register-offset instructions,
which were extremely dodgy beforehand: even when the instruction used
wM, LLVM's model had xM as an operand. We papered over this
discrepancy before, but that approach doesn't work now so I split them
into separate X and W variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209425 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-22 11:56:09 +00:00
Bradley Smith
bdc6a7a506 [ARM64] Port basic-a64-diagnostics.s over to ARM64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209207 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-20 13:33:41 +00:00
Tim Northover
c9ff20e8c6 TableGen: convert InstAlias's Emit bit to an int.
When multiple aliases overlap, the correct string to print can often be
determined purely by considering the InstAlias declarations in some particular
order. This allows the user to specify that order manually when desired,
without resorting to hacking around with the default lexicographical order on
Record instantiation, which is error-prone and ugly.

I was also mistaken about "add w2, w3, w4" being the same as "add w2, w3, w4,
uxtw". That's only true if Rn is the stack pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209199 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-20 09:17:16 +00:00
Tim Northover
a9a94ce839 TableGen: fix operand counting for aliases
TableGen has a fairly dubious heuristic to decide whether an alias should be
printed: does the alias have lest operands than the real instruction. This is
bad enough (particularly with no way to override it), but it should at least be
calculated consistently for both strings.

This patch implements that logic: first get the *correct* string for the
variant, in the same way as the Matcher, without guessing; then count the
number of whitespace chars.

There are basically 4 changes this brings about after the previous
commits; all of these appear to be good, so I have changed the tests:

+ ARM64: we print "neg X, Y" instead of "sub X, xzr, Y".
+ ARM64: we skip implicit "uxtx" and "uxtw" modifiers.
+ Sparc: we print "mov A, B" instead of "or %g0, A, B".
+ Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208969 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-16 09:42:04 +00:00
Tim Northover
0a088b1fc5 ARM64: print correct aliases for NEON mov & mvn instructions
In all cases, if a "mov" alias exists, it is the canonical form of the
instruction. Now that TableGen can support aliases containing syntax variants,
we can enable them and improve the quality of the asm output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 12:11:02 +00:00
Tim Northover
f61a467a59 TableGen/ARM64: print aliases even if they have syntax variants.
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 11:16:32 +00:00
Bradley Smith
dbe4f8b96e [ARM64] Add/Fixup diagnostics for floating point immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15 11:07:28 +00:00
Tim Northover
d6cd0381f6 TableGen: use PrintMethods to print more aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-12 18:04:06 +00:00
Tim Northover
4d28f030f7 AArch64/ARM64: add two more MC tests to ARM64 set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208085 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:58 +00:00
Tim Northover
c08733f867 AArch64/ARM64: enable MC-level diagnostic tests for NEON insts.
Obviously we can't expect the two backends to produce identical diagnostics,
since what's possible depends quite a bit on how the .td files are structured.
I think the ARM64 diagnostics are basically of the same quality in all the
changed cases, so I've split the CHECK lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208084 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 12:50:55 +00:00
Tim Northover
f2f35a9ca3 AArch64/ARM64: print BFM instructions as BFI or BFXIL
The canonical form of the BFM instruction is always one of the more explicit
extract or insert operations, which makes reading output much easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:29:38 +00:00
Hans Wennborg
a8febf2283 ELFObjectWriter: deduplicate suffices in strtab
We already do this for shstrtab, so might as well do it for strtab. This
extracts the string table building code into a separate class. The idea
is to use it for other object formats too.

I mostly wanted to do this for the general principle, but it does save a
little bit on object file size. I tried this on a clang bootstrap and
saved 0.54% on the sum of object file sizes (1.14 MB out of 212 MB for
a release build).

Differential Revision: http://reviews.llvm.org/D3533

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:25:02 +00:00
Tim Northover
83286f081d AArch64/ARM64: implement remaining TLS relocations (purely MC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207668 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:26 +00:00
Tim Northover
50de5e4f57 AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207667 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:20 +00:00
Tim Northover
52f60f81d9 AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"
It's been decided that in the future, the floating-point immediate in
instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which
has been implemented on AArch64 already but not ARM64.

This fixes that issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207666 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:07 +00:00
Tim Northover
ee053f4f51 ARM64: enable AArch64's basic-a64-instructions test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:10 +00:00
Tim Northover
d8b6fe2c41 AArch64/ARM64: add ARM64 runs to more MC tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207120 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 15:04:26 +00:00
Tim Northover
7b59710b6f AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too.
This skips a couple of compare ones due to the different syntaxt for
floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle
ARM64 to make it work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207119 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 15:04:20 +00:00
Tim Northover
a05d37e1f4 AArch64: print NEON lists with a space.
This matches ARM64 behaviour, which I think is clearer. It also puts all the
churn from that difference into one easily ignored commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 14:06:20 +00:00
Tim Northover
c80e56729b AArch64/ARM64: enable remaining MC elf tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207112 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:41 +00:00
Tim Northover
d4daf1762d AArch64/ARM64: allow negative addends, at least on ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207111 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:38 +00:00
Tim Northover
421c65b9b4 ARM64: support relocated "TBZ/TBNZ" instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:34 +00:00
Tim Northover
332497fc56 AArch64/ARM64: support relocated ADR instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207109 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:30 +00:00
Tim Northover
4fec4077fc AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiers
We only need assembly support, so it's fairly easy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207108 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:56:27 +00:00
Tim Northover
d4b4f400e8 AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands
These can have different relocations in ELF. In particular both:

    b.eq global
    ldr x0, global

are valid, giving different relocations. The only possible way to distinguish
them is via a different fixup, so the operands had to be separated throughout
the backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207105 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:12:10 +00:00
Tim Northover
92f4b34653 AArch64/ARM64: enable some MC tests on ARM64
This will also (as with CodeGen) disable testing when the ARM64 backend is not
present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-24 12:12:01 +00:00