Commit Graph

91748 Commits

Author SHA1 Message Date
Akira Hatanaka
cd6c57917d [mips] Instruction selection patterns for DSP-ASE vector select and compare
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 22:37:26 +00:00
Adrian Prantl
86a87d9ba1 Temporarily revert "Change the informal convention of DBG_VALUE so that we can express a"
because it breaks some buildbots.

This reverts commit 180816.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180819 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 22:35:14 +00:00
Adrian Prantl
a2b56692c8 Change the informal convention of DBG_VALUE so that we can express a
register-indirect address with an offset of 0.
It used to be that a DBG_VALUE is a register-indirect value if the offset
(operand 1) is nonzero. The new convention is that a DBG_VALUE is
register-indirect if the first operand is a register and the second
operand is an immediate. For plain registers use the combination reg, reg.

rdar://problem/13658587

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180816 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 22:16:46 +00:00
Andrew Trick
f13fc1b23a MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.
I'll fix the heuristic in a general way in a follow-up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180815 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 22:10:59 +00:00
Akira Hatanaka
13ec4812fc [mips] Simplify code.
No intended functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 21:17:07 +00:00
Nadav Rotem
7fac0ef71c Fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180806 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 21:04:51 +00:00
Nadav Rotem
6f4888f259 Update the release notes about the min/max reductions that Arnold added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180805 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 21:04:04 +00:00
Akira Hatanaka
b8b1d35743 [mips] Test for r179873.
Patch by Zoran Jovanovic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 20:48:49 +00:00
Jim Grosbach
6548096a2e InstCombine: Fold more shuffles of shuffles.
Always fold a shuffle-of-shuffle into a single shuffle when there's only one
input vector in the first place. Continue to be more conservative when there's
multiple inputs.

rdar://13402653
PR15866

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 20:43:52 +00:00
Akira Hatanaka
b0caf5ff64 [mips] Clear isCommutable bit of instructions which are not commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180801 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 20:40:39 +00:00
Hal Finkel
db31bd31d6 LocalStackSlotAllocation improvements
First, taking advantage of the fact that the virtual base registers are allocated in order of the local frame offsets, remove the quadratic register-searching behavior. Because of the ordering, we only need to check the last virtual base register created.

Second, store the frame index in the FrameRef structure, and get the frame index and the local offset from this structure at the top of the loop iteration. This allows us to de-nest the loops in insertFrameReferenceRegisters (and I think makes the code cleaner). I also moved the needsFrameBaseReg check into the first loop over instructions so that we don't bother pushing FrameRefs for instructions that don't want a virtual base register anyway.

Lastly, and this is the only functionality change, avoid the creation of single-use virtual base registers. These are currently not useful because, in general, they end up replacing what would be one r+r instruction with an add and a r+i instruction. Committing this removes the XFAIL in CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll

Jim has okayed this off-list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180799 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 20:04:37 +00:00
Rafael Espindola
34f39841d3 Text files should not be marked executable.
Patch by Oliver Pinter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 19:06:15 +00:00
Manman Ren
2dc50d3067 TBAA: remove !tbaa from testing cases if not used.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 17:52:57 +00:00
Adrian Prantl
8960a5c63d Spelling. Thanks, Eric.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180794 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 17:33:32 +00:00
Adrian Prantl
8b11e89b93 Set debug locations for branch instructions created during inlining, even
the inlined function has multiple returns.

rdar://problem/12415623

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 17:08:16 +00:00
Rafael Espindola
76f103e021 Change getSlotIndex to return unsigned.
The actual storage was already using unsigned, but the interface was using
uint64_t. This is wasteful on 32 bits and looks to be the root causes of
a miscompilation on Windows where a value was being sign extended to 64bits
to compare with the result of getSlotIndex.

Patch by Pasi Parviainen!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180791 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 16:53:38 +00:00
Rafael Espindola
e87dadc44b Fix Addend computation for non external relocations on Macho.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 15:40:54 +00:00
Vincent Lejeune
1872730c5a R600: fix loop-address.ll test
Texture cache is now used when shader type is not specified

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180785 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 12:47:56 +00:00
David Majnemer
527db3f26b Fix a bug in foldSelectICmpAndOr.
Differences in bitwidth between X and Y could exist even if C1 and C2 have
the same Log2 representation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 10:36:33 +00:00
Mihai Popa
62d77858be s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 09:00:12 +00:00
David Majnemer
defce4cfd6 Fix "Combine bit test + conditional or into simple math"
This fixes the optimization introduced in r179748 and reverted in r179750.

While the optimization was sound, it did not properly respect differences in
bit-width.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180777 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 08:57:58 +00:00
Michael Liao
8838410a75 Rewrite X86 codegen regression test with FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180776 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 07:51:08 +00:00
Stepan Dyatkovskiy
f65e4932f8 Refactoring patch.
1. VarArgStyleRegisters: functionality that emits "store" instructions for byval regs moved out into separated method "StoreByValRegs". Before this patch VarArgStyleRegisters had confused use-cases. It was used for both variadic functions and for regular functions with byval parameters. In last case it created new stack-frame and registered it as VarArg frame, that is wrong.

This patch replaces VarArgsStyleRegisters usage for byval parameters with StoreByValRegs method.

2. In ARMMachineFunctionInfo, "get/setVarArgsRegSaveSize" was renamed to "get/setArgRegsSaveSize". By the same reason. Sometimes it was used for variadic functions, and sometimes for byval parameters in regular functions. Actually, this property means the size of registers, that keeps arguments, and thats why it was renamed.

3. In ARMISelLowering.cpp, ARMTargetLowering class, in methods computeRegArea and StoreByValRegs, VARegXXXXXX was renamed to ArgRegsXXXXXX still by the same reasons.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 07:19:58 +00:00
Reid Kleckner
2a83943855 Try to fix ProgramTest on FreeBSD
This seemed like the cleanest way to find the test executable.  Also fix
the file mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180770 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 04:30:41 +00:00
Rafael Espindola
8e6e02a41b Collect the Addend for external relocs.
This fixes 2013-04-04-RelocAddend.ll. We don't have a testcase for non external
relocs with an Addend. I will try to write one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180767 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 01:29:57 +00:00
Vincent Lejeune
4fb224e3bd R600: Always use texture cache for compute shaders
This will improve the performance of memory reads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:44 +00:00
Vincent Lejeune
2c836f84db R600: use native for alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:38 +00:00
Vincent Lejeune
25f259cde2 R600: Packetize instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:27 +00:00
Vincent Lejeune
abcde265b1 R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:17 +00:00
Vincent Lejeune
e332e3559b R600: Add a Bank Swizzle operand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:08 +00:00
Vincent Lejeune
7097b1ddea R600: Take inner dependency into tex/vtx clauses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:14:00 +00:00
Vincent Lejeune
b6379de427 R600: Turn TEX/VTX into native instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:53 +00:00
Vincent Lejeune
631591e6f3 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:39 +00:00
Michael Liao
7d8ea50b93 Rewrite test in FileCheck instead of grep in X86 codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180754 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:38 +00:00
Vincent Lejeune
0dc415cf28 R600: Add some new processor variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180753 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:27 +00:00
Vincent Lejeune
8723c9ebf5 R600: Clean up instruction class definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180752 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:20 +00:00
Vincent Lejeune
86cdb70417 R600: config section now reports use of killgt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-30 00:13:13 +00:00
Bill Wendling
725dae5791 Revert the command line option patch. However, keep the part that makes this pass on Windows. I.e., we don't emit the target dependent attributes in a comment before the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 23:48:06 +00:00
Manman Ren
ff6222ef2f TBAA: remove !tbaa from testing cases if not used.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180745 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:58:55 +00:00
Bill Wendling
ad96c64355 Duplicate a testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:42:47 +00:00
Manman Ren
e78d832097 TBAA: remove !tbaa from testing cases if not used.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180743 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:42:01 +00:00
Michael Liao
26ebdd1e7c Rewrite some tests with FileCHeck in X86 codegen
- Revise previous patches of the same purpose by fixing
  *) grep <PA> | not grep <PB> semantically is not the same as
     CHECK: <PA>{{^<PB>.*$}} as the former will check all occurrences of <PA>
     while the later only check the first match. As the result, CHECK needs
     putting in all place where <PA> occurs.
  *) grep <PA> | count <N> needs a final CHECK-NOT of the same pattern.
     (As 'CHECK-<N>' is proposed for discussion, converting 'grep | count <N>'
      where N > 1 is postponed.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:41:29 +00:00
Adrian Prantl
3e3456b23a Improve documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180738 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:25:52 +00:00
Bill Wendling
fa2eac54e6 Emit the TLS initialization function pointers into the correct section.
The `llvm.tls_init_funcs' (created by the front-end) holds pointers to the TLS
initialization functions. These need to be placed into the correct section so
that they are run before `main()'.

<rdar://problem/13733006>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:25:40 +00:00
Rafael Espindola
59a0e79631 Add getSymbolAlignment to the ObjectFile interface.
For regular object files this is only meaningful for common symbols. An object
file format with direct support for atoms should be able to provide alignment
information for all symbols.

This replaces getCommonSymbolAlignment and fixes
test-common-symbols-alignment.ll on darwin. This also includes a fix to
MachOObjectFile::getSymbolFlags. It was marking undefined symbols as common
(already tested by existing mcjit tests now that it is used).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180736 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:24:22 +00:00
Tom Stellard
d8b2da1136 R600: Use correct CF_END instruction on Northern Island GPUs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:23:58 +00:00
Tom Stellard
015f586bc9 R600: Fix encoding of CF_END_{EG, R600} instructions
The EOP bit was not being encoded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:23:54 +00:00
Rafael Espindola
8393b99ed0 Rationalize what is public in RuntimeDyldMachO and RuntimeDyldELF.
The implemented RuntimeDyldImpl interface is public. Everything else is private.
Since these classes are not inherited from (yet), there is no need to have
protected members.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180733 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 22:06:33 +00:00
Arnold Schwaighofer
8228ffe72d SimplifyCFG: If convert single conditional stores
This resurrects r179957, but adds code that makes sure we don't touch
atomic/volatile stores:

This transformation will transform a conditional store with a preceeding
uncondtional store to the same location:

 a[i] =
 may-alias with a[i] load
 if (cond)
   a[i] = Y

into an unconditional store.

 a[i] = X
 may-alias with a[i] load
 tmp = cond ? Y : X;
 a[i] = tmp

We assume that on average the cost of a mispredicted branch is going to be
higher than the cost of a second store to the same location, and that the
secondary benefits of creating a bigger basic block for other optimizations to
work on outway the potential case where the branch would be correctly predicted
and the cost of the executing the second store would be noticably reflected in
performance.

hmmer's execution time improves by 30% on an imac12,2 on ref data sets. With
this change we are on par with gcc's performance (gcc also performs this
transformation). There was a 1.2 % performance improvement on a ARM swift chip.
Other tests in the test-suite+external seem to be mostly uninfluenced in my
experiments:
This optimization was triggered on 41 tests such that the executable was
different before/after the patch. Only 1 out of the 40 tests (dealII) was
reproducable below 100% (by about .4%). Given that hmmer benefits so much I
believe this to be a fair trade off.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180731 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 21:28:24 +00:00
Rafael Espindola
8a905e7e34 Disable the MCJIT tests on 32 bit darwin.
I recently enabled them on 32 and 64 bit darwin, but it looks like 32 bit is
still fairly broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180730 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-29 21:09:32 +00:00