Commit Graph

99471 Commits

Author SHA1 Message Date
Tim Northover
6849f102ca ARM: add constraint that RdLo != Rn != RdHi for v5 MLA insts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199212 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 13:05:47 +00:00
Tim Northover
6e533d710d ARM: remove unused UMAALv5 node
It was incorrect anyway, since it didn't have accumulator inputs and wasn't
even supported on v5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199211 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 13:05:42 +00:00
Nico Rieck
55463f4ec1 Revert "Decouple dllexport/dllimport from linkage"
Revert this for now until I fix an issue in Clang with it.

This reverts commit r199204.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199207 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 12:38:32 +00:00
Nico Rieck
62b811443d Revert "Handle dllexport for global aliases"
This reverts commit r199205.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199206 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 12:36:54 +00:00
Nico Rieck
f32b968e7f Handle dllexport for global aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199205 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 11:55:40 +00:00
Nico Rieck
bce07a0c3b Decouple dllexport/dllimport from linkage
Representing dllexport/dllimport as distinct linkage types prevents using
these attributes on templates and inline functions.

Instead of introducing further mixed linkage types to include linkonce and
weak ODR, the old import/export linkage types are replaced with a new
separate visibility-like specifier:

  define available_externally dllimport void @f() {}
  @Var = dllexport global i32 1, align 4

Linkage for dllexported globals and functions is now equal to their linkage
without dllexport. Imported globals and functions must be either
declarations with external linkage, or definitions with
AvailableExternallyLinkage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199204 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 11:55:03 +00:00
Nico Rieck
1b1321f080 Fix fastcall mangling of dllimported symbols
fastcall requires @ as global prefix instead of _ but getNameWithPrefix
wrongly assumes the OutName buffer is empty and replaces at index 0.
For imported functions this buffer is pre-filled with "__imp_" resulting
in broken "@_imp_foo@0" mangling.

Instead replace at the proper index. We also never have to prepend the
@-prefix because this fastcall mangling is only used on 32-bit Windows
targets which have _ has global prefix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199203 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 11:53:26 +00:00
NAKAMURA Takumi
d13b9da1b6 Revert r199191, "LTO: add API to set strategy for -internalize"
Please update also Other/link-opts.ll, in next time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 09:40:18 +00:00
Craig Topper
8e31bc35ec Remove stray comma in enum to satisfy -Wpedantic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199194 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 08:07:10 +00:00
Craig Topper
525ae45240 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199193 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 07:41:20 +00:00
Duncan P. N. Exon Smith
67af0456bc LTO: add API to set strategy for -internalize
Add API to LTOCodeGenerator to specify a strategy for the -internalize
pass.

This is a new attempt at Bill's change in r185882, which he reverted in
r188029 due to problems with the gold linker.  This puts the onus on the
linker to decide whether (and what) to internalize.

In particular, running internalize before outputting an object file may
change a 'weak' symbol into an internal one, even though that symbol
could be needed by an external object file --- e.g., with arclite.

This patch enables three strategies:

- LTO_INTERNALIZE_FULL: the default (and the old behaviour).
- LTO_INTERNALIZE_NONE: skip -internalize.
- LTO_INTERNALIZE_HIDDEN: only -internalize symbols with hidden
  visibility.

LTO_INTERNALIZE_FULL should be used when linking an executable.

Outputting an object file (e.g., via ld -r) is more complicated, and
depends on whether hidden symbols should be internalized.  E.g., for
ld -r, LTO_INTERNALIZE_NONE can be used when -keep_private_externs, and
LTO_INTERNALIZE_HIDDEN can be used otherwise.  However,
LTO_INTERNALIZE_FULL is inappropriate, since the output object file will
eventually need to link with others.

lto_codegen_set_internalize_strategy() sets the strategy for subsequent
calls to lto_codegen_write_merged_modules() and lto_codegen_compile*().

<rdar://problem/14334895>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199191 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 06:37:26 +00:00
Jakob Stoklund Olesen
5b8e04cd71 Always let value types influence register classes.
When creating a virtual register for a def, the value type should be
used to pick the register class. If we only use the register class
constraint on the instruction, we might pick a too large register class.

Some registers can store values of different sizes. For example, the x86
xmm registers can hold f32, f64, and 128-bit vectors. The three
different value sizes are represented by register classes with identical
register sets: FR32, FR64, and VR128. These register classes have
different spill slot sizes, so it is important to use the right one.

The register class constraint on an instruction doesn't necessarily care
about the size of the value its defining. The value type determines
that.

This fixes a problem where InstrEmitter was picking 32-bit register
classes for 64-bit values on SPARC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199187 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 06:18:38 +00:00
Jakob Stoklund Olesen
aaf6cbdc7e Switch the NEON register class from QPR to DPair.
The already allocatable DPair superclass contains odd-even D register
pair in addition to the even-odd pairs in the QPR register class. There
is no reason to constrain the set of D register pairs that can be used
for NEON values. Any NEON instructions that require a Q register will
automatically constrain the register class to QPR.

The allocation order for DPair begins with the QPR registers, so
register allocation is unlikely to change much.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199186 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 06:18:34 +00:00
Chandler Carruth
87a390ab47 [PM] Fix stale header blocker, found by Duncan Smith in code review!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199185 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 05:50:19 +00:00
Chandler Carruth
64aabee38e Remove the last weird subproject, 'privbracket'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199183 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 05:05:18 +00:00
Chandler Carruth
7ba06ede59 Add checks to configure for sufficiently modern host compilers. This
requires Clang 3.1 or GCC 4.7. If the compiler isn't Clang or GCC, we
don't try to do any sanity checking, but this give us at least
a reasonable baseline of modern compilers.

Also, I'm not claiming that this is the best way to do compiler version
tests. I'm happy for anyone to suggest better ways of doing this test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199182 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 05:02:38 +00:00
Rafael Espindola
3c733ea064 Replace .mips_hack_stocg with ".set micromips" and ".set nomicromips".
This matches what gnu as does and implementing this is easier than arguing
about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199181 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 04:25:13 +00:00
Mark Seaborn
dfa550a176 Fix llc to not reuse spill slots in functions that invoke setjmp()
We need to ensure that StackSlotColoring.cpp does not reuse stack
spill slots in functions that call "returns_twice" functions such as
setjmp(), otherwise this can lead to miscompiled code, because a stack
slot would be clobbered when it's still live.

This was already handled correctly for functions that call setjmp()
(though this wasn't covered by a test), but not for functions that
invoke setjmp().

We fix this by changing callsFunctionThatReturnsTwice() to check for
invoke instructions.

This fixes PR18244.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199180 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 04:20:01 +00:00
Chandler Carruth
3f7ae00155 Ok, really, for the last time, llvm-gcc is dead Jim.
Also, so is stacker, llvm-tv, etc. Wow.

But will someone please fess up to what projects/privbracket is and why
our autoconf build supports it?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199179 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 04:01:01 +00:00
Chandler Carruth
5b45789afd llvm-gcc is dead. REALLY. IT'S DEAD JIM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199178 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 03:46:00 +00:00
Rafael Espindola
e99ebe7d0c Make getTargetStreamer return a possibly null pointer.
This will allow it to be called from target independent parts of the main
streamer that don't know if there is a registered target streamer or not. This
in turn will allow targets to perform extra actions at specified points in the
interface: add extra flags for some labels, extra work during finalization, etc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199174 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-14 01:21:46 +00:00
Duncan P. N. Exon Smith
f619e9039a Remove extra } in documentation comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199162 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 23:11:48 +00:00
Cameron McInally
9ad2161ea7 Clean up RUN command for Assembler/getInt.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199158 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 22:37:35 +00:00
Chandler Carruth
55e6c6184a Factor the option and checking of compiler version better. Put the
option with the others in the top level CMakeLists, and put the check in
HandleLLVMOptions. This will also let it be used from the standalone
Clang builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199149 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 22:21:34 +00:00
Chandler Carruth
d00ec5ef7b Raise the minimum CMake version to 2.8.8 -- we have a report that the
compiler version checking doesn't work on 2.8.7. This feature was
documented in 2.8.10, but existed for an unknown amount of time before
that.

I'm actually happy to revert this and remove the use of the feature if
there is anyone with a specific problem updating CMake. Please just let
me know. I don't want to re-implement this CMake functionality unless
there is a reason, and this is the only real way to find that out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 22:05:20 +00:00
Cameron McInally
486fdf2e65 Fix uninitialized warning in llvm/lib/IR/DataLayout.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199147 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 22:04:55 +00:00
Juergen Ributzka
df7e862802 [DAG] Refactor ReassociateOps - no functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199146 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 21:49:25 +00:00
Chandler Carruth
bf2609e264 Add a check that the host compiler is modern to CMake, take 1. This is
likely to be reverted and re-applied a few times. The minimum versions
we're aiming at:

  GCC 4.7
  Clang 3.1
  MSVC 17.0 (Visual Studio 2012)

Let me know if something breaks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199145 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 21:47:35 +00:00
Juergen Ributzka
298d1a6b21 [DAG] Teach DAG to also reassociate vector operations
This commit teaches DAG to reassociate vector ops, which in turn enables
constant folding of vector op chains that appear later on during custom lowering
and DAG combine.

Reviewed by Andrea Di Biagio

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199135 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 20:51:35 +00:00
Andrew Trick
de0847d6a5 Hide the pre-RA-sched= option.
This is a very confusing option for a feature that will go away.

-enable-misched is exposed instead to help triage issues with the new
scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199133 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 20:08:27 +00:00
Weiming Zhao
436f2975ac Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks
The issue is caused when Post-RA scheduler reorders a bundle instruction
(IT block). However, it only flips the CPSR liveness of the bundle instruction,
leaves the instructions inside the bundle unchanged, which causes inconstancy and crashes
Thumb2SizeReduction.cpp::ReduceMBB().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199127 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 18:47:54 +00:00
Rafael Espindola
99c7fec2c9 Update getLazyBitcodeModule to use ErrorOr for error handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199125 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 18:31:04 +00:00
Andrea Di Biagio
36713c2c0a [AArch64] Fix assertion failure caused by an invalid comparison between APInt values.
APInt only knows how to compare values with the same BitWidth and asserts
in all other cases.

With this fix, function PerformORCombine does not use the APInt equality
operator if the APInt values returned by 'isConstantSplat' differ in BitWidth.
In that case they are different and no comparison is needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199119 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 16:51:00 +00:00
Joerg Sonnenberger
286cc13546 Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199118 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 15:50:36 +00:00
Richard Sandiford
91e35c7533 [SystemZ] Flesh out stackrestore test (frame-11.ll)
...so that it does something vaguely sensible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199117 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 15:44:44 +00:00
Richard Sandiford
dcbd7ca4a7 [SystemZ] Add "volatile" to a dead store in variable-loc.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199116 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 15:42:16 +00:00
Richard Sandiford
be110d99db [SystemZ] Improve risbg-01.ll test
The old mask in f24 wasn't well chosen because the lshr would always be zero.
CodeGen didn't detect this but InstCombine would.  The new mask ensures
that both shifts are needed.

f26 is specifically testing for a wrap-around mask.  The AND can be applied
to just the shift left, either before or after the shift.  Again, CodeGen
kept it in the original form but InstCombine would mask after the shift
instead.  The exact choice of NILF isn't important for the test so I just
dropped it and kept the rotate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199115 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 15:40:25 +00:00
Richard Sandiford
80a3301b37 [SystemZ] Optimize (sext (ashr (shl ...), ...))
...into (ashr (shl (anyext X), ...), ...), which requires one fewer
instruction.  The (anyext X) can sometimes be simplified too.

I didn't do this in DAGCombiner because widening shifts isn't a win
on all targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199114 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 15:17:53 +00:00
Chris Lattner
1023a9492f fix a -Wdocumentation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199113 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 15:10:11 +00:00
Tim Northover
dc408573c4 ARM: add test for r199108. Oops.
rdar://problem/15800156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199109 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 14:20:25 +00:00
Tim Northover
08a8edb848 ARM: constrain Thumb LDRLIT pseudo-instructions to r0-r7.
Previously we only used GPR for the destination placeholder in "ldr rD, [pc,
incorrect codegen under the integrated assembler.

This should fix both issues (which probably only affect MachO targets at the
moment).

rdar://problem/15800156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199108 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 14:19:17 +00:00
David Woodhouse
f71254859e [x86] Fix retq/retl handling in 64-bit mode
This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.

LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:

asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");

cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.

I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199106 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 14:05:59 +00:00
Chandler Carruth
7f2eff792a [PM] Split DominatorTree into a concrete analysis result object which
can be used by both the new pass manager and the old.

This removes it from any of the virtual mess of the pass interfaces and
lets it derive cleanly from the DominatorTreeBase<> template. In turn,
tons of boilerplate interface can be nuked and it turns into a very
straightforward extension of the base DominatorTree interface.

The old analysis pass is now a simple wrapper. The names and style of
this split should match the split between CallGraph and
CallGraphWrapperPass. All of the users of DominatorTree have been
updated to match using many of the same tricks as with CallGraph. The
goal is that the common type remains the resulting DominatorTree rather
than the pass. This will make subsequent work toward the new pass
manager significantly easier.

Also in numerous places things became cleaner because I switched from
re-running the pass (!!! mid way through some other passes run!!!) to
directly recomputing the domtree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 13:07:17 +00:00
Chandler Carruth
bb4954ddbf [PM][cleanup] Clean up comments and use modern doxygen in this file.
This is a precursor to breaking the pass that computes the DominatorTree
apart from the concrete DominatorTree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199103 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 13:06:58 +00:00
Elena Demikhovsky
1f044d443d AVX-512: Embedded Rounding Control - encoding and printing
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199102 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 12:55:03 +00:00
Chandler Carruth
ed0b9ad2e6 [PM] Fix the const-correctness of the generic DominatorTreeBase to
support notionally const queries even though they may trigger DFS
numbering updates.

The updating of DFS numbers and tracking of slow queries do not mutate
the observable state of the domtree. They should be const to
differentiate them from the APIs which mutate the tree directly to do
incremental updates.

This will make it possible in a world where the DominatorTree is not
a pass but merely the result of running a pass to derive DominatorTree
from the base class as it was originally designed, removing a huge
duplication of API in DominatorTree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199101 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 11:58:34 +00:00
Chandler Carruth
2073b0a63c [PM] Pull the generic graph algorithms and data structures for dominator
trees into the Support library.

These are all expressed in terms of the generic GraphTraits and CFG,
with no reliance on any concrete IR types. Putting them in support
clarifies that and makes the fact that the static analyzer in Clang uses
them much more sane. When moving the Dominators.h file into the IR
library I claimed that this was the right home for it but not something
I planned to work on. Oops.

So why am I doing this? It happens to be one step toward breaking the
requirement that IR verification can only be performed from inside of
a pass context, which completely blocks the implementation of
verification for the new pass manager infrastructure. Fixing it will
also allow removing the concept of the "preverify" step (WTF???) and
allow the verifier to cleanly flag functions which fail verification in
a way that precludes even computing dominance information. Currently,
that results in a fatal error even when you ask the verifier to not
fatally error. It's awesome like that.

The yak shaving will continue...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199095 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 10:52:56 +00:00
Tim Northover
eaefef43d7 Revert "ReMat: fix overly cavalier attitude to sub-register indices"
Very sorry, this was a premature patch that I still need to investigate and
finish off (for some reason beyond me at the moment it doesn't actually fix the
issue in all cases).

This reverts commit r199091.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199093 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 10:49:11 +00:00
Tim Northover
a917400584 Docs: fix sign of division and increase equivocation on code generated.
I should have been a politician.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199092 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 10:47:04 +00:00
Tim Northover
54d3aa1537 ReMat: fix overly cavalier attitude to sub-register indices
There are two attempted optimisations in reMaterializeTrivialDef, trying to
avoid promoting the size of a register too much when rematerializing.
Unfortunately, both appear to be flawed. First, we see if the original register
would have worked, but this is inadequate. Consider:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0 = COPY v1:Q1 (v1, v2 are QQ)
    ...
    uses of v2

In this case even though v2 *could* be used directly as the output of
SOMETHING, this would set the wrong bits of the QQ register involved. The
correct rematerialization must be:

    v2:Q0_Q1 = SOMETHING (v2 promoted to QQQ)
    ...
    uses of v2:Q1_Q2

For the second optimisation, if the correct remat is "v2:idx = SOMETHING" then
we can't necessarily expect v2 itself to be valid for SOMETHING, but we do try
to hunt for a class between v1 and v2 that works. Unfortunately, this is also
wrong:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0_Q1 = COPY v1 (v1 is QQ, v2 is QQQ)
    ...
    uses of v2 as a QQQ

The canonical rematerialization here is "v2:Q0_Q1 = SOMETHING". However current
logic would decide that v2 could be a QQ (no interest is taken in later uses).

This patch, therefore, always accepts the widened register class without trying
to be clever. Generally there is no penalty to this (e.g. in the common GR32 <
GR64 case, expanding the width doesn't matter because it's not like you were
going to do anything else with the high bits of a GR32 register). It can
increase register pressure in cases like the ARM VFP regs though (multiple
non-overlapping but equivalent subregisters). Hopefully this situation is rare
enough that it won't matter.

Unfortunately, no in-tree targets actually expose this as far as I can tell
(there are so few isAsCheapAsAMove instructions for it to trigger on) so I've
been unable to produce a test. It was exposed in our ARM64 SPEC tests though,
and I will be adding a test there that we should be able to contribute
soon(TM).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199091 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-13 10:47:01 +00:00