6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-28 20:29:21 +00:00
Code Issues Projects Releases Wiki Activity
96,476 Commits 39 Branches 0 Tags 277 MiB
d1bd8d904c
Commit Graph

26363 Commits

Author SHA1 Message Date
Matthias Braun
d1bd8d904c ARM: optimizeSelect has to consider the previous register class 
optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191963 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 16:52:56 +00:00
Matthias Braun
4e54f41d6c ARM: do not add a regmask for TAILJUMPs 
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191962 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 16:52:54 +00:00
Matthias Braun
e1bde51d63 ARM: preserve undef flag in pseudo instruction expanders 
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191961 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 16:52:51 +00:00
Jiangning Liu
dd518bcc9d Implement aarch64 neon instruction set AdvSIMD (3V elem). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 09:20:44 +00:00
Elena Demikhovsky
5086ff1320 AVX-512: Fixed encoding of VMOVQ instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191889 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 12:03:26 +00:00
Amara Emerson
6eef361b73 [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly. 
Patch by Artyom Skrobov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 09:31:51 +00:00
Craig Topper
198f1b340a Replace C++ style comment with a C style comment to satisfy some of the build bots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191880 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 06:29:59 +00:00
Craig Topper
e3b0a9c51a Remove comma from the end of an enum. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191877 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 06:18:26 +00:00
Craig Topper
279d28265d Add XOP disassembler support. Fixes PR13933. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 05:17:48 +00:00
Craig Topper
fafe4bbd6c Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-03 04:16:45 +00:00
Vincent Lejeune
a2f1317f09 R600: Add a ldptr intrinsic to support MSAA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191838 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-02 16:00:33 +00:00
Elena Demikhovsky
c699417f11 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-02 12:20:42 +00:00
Elena Demikhovsky
d243c19c1f AVX-512: Added TB prefix to all instructions without prefixes, 
otherwise encoding fails after the last change in X86MCCodeEmitter.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-02 06:39:07 +00:00
Vincent Lejeune
dfef7cbfc6 R600: add a pass that merges clauses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 19:32:58 +00:00
Vincent Lejeune
c6c37d74a2 R600: Put PRED_X instruction in its own clause 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191789 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 19:32:49 +00:00
Vincent Lejeune
5b00e833fa R600: Enable -verify-machineinstrs in some tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 19:32:38 +00:00
Richard Sandiford
e22c56d6d8 [SystemZ] Add comparisons of high words and memory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 15:00:44 +00:00
Richard Sandiford
185ef05ad6 [SystemZ] Add comparisons of large immediates using high words 
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191775 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:56:23 +00:00
Richard Sandiford
ad366a3f67 [SystemZ] Add immediate addition involving high words 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191774 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:53:46 +00:00
Richard Sandiford
bd1958d8e9 [SystemZ] Extend test-under-mask support to high GR32s 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:41:52 +00:00
Richard Sandiford
f985f01574 [SystemZ] Extend 32-bit RISBG optimizations to high words 
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191770 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:36:20 +00:00
Richard Sandiford
00f5335ea0 [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words 
As the comment says, we always want to use STOC for 32-bit stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191767 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:33:55 +00:00
Tim Northover
bba9390fc6 ARM: support interrupt attribute 
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.

rdar://problem/14207019

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:33:28 +00:00
Richard Sandiford
5fb8d3144f [SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and above 
Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers.  This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191764 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:31:11 +00:00
Richard Sandiford
b9dcca8265 [SystemZ] Allow integer AND involving high words 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191762 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:20:41 +00:00
Richard Sandiford
1ff62e182e [SystemZ] Allow integer XOR involving high words 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191759 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 14:08:44 +00:00
Rafael Espindola
8819c84aed Remove several unused variables. 
Patch by Alp Toker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191757 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:32:03 +00:00
Richard Sandiford
1c831f7f1f [SystemZ] Allow integer OR involving high words 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191755 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:22:41 +00:00
Richard Sandiford
645d250b84 [SystemZ] Allow integer insertions with a high-word destination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191753 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:18:56 +00:00
Richard Sandiford
4708657097 [SystemZ] Allow selects with a high-word destination 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191751 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:10:16 +00:00
Richard Sandiford
4c8feae136 [SystemZ] Add patterns to load a constant into a high word (IIHF) 
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191750 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:02:28 +00:00
Joey Gouly
441aeddd56 [ARM] Remove an unused function from the disassembler. 
Pointed out by Joerg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191749 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 13:01:10 +00:00
Matheus Almeida
5537013350 Test commit. Updated comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191748 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 12:53:00 +00:00
Richard Sandiford
79e2ed4d83 [SystemZ] Add register zero extensions involving at least one high word 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191746 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 12:49:07 +00:00
Joey Gouly
d1311ac171 [ARM] Introduce the 'sevl' instruction in ARMv8. 
This also removes the restriction on the immediate field of the 'hint'
instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 12:39:11 +00:00
Richard Sandiford
9813dbf396 [SystemZ] Add truncating high-word stores (STCH and STHH) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191743 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 12:22:49 +00:00
Richard Sandiford
9a05f040e7 [SystemZ] Add zero-extending high-word loads (LLCH and LLHH) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191742 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 12:19:08 +00:00
Richard Sandiford
ced450f0e6 [SystemZ] Add sign-extending high-word loads (LBH and LHH) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191740 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 12:11:47 +00:00
Richard Sandiford
55d7d83b6c [SystemZ] Use upper words of GR64s for codegen 
This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store).  The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.

The easiest way of testing this seemed to be add a new "h" register
constraint for high words.  I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191739 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 11:26:28 +00:00
Richard Sandiford
7d0b89bedd [SystemZ] Reapply: Add definitions of LFH and STFH 
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191738 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 10:31:04 +00:00
Daniel Sanders
7f768e0368 [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191737 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 10:22:35 +00:00
Vladimir Medic
d59ad8a801 This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191734 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 09:48:56 +00:00
Elena Demikhovsky
c8d0d00781 AVX-512: Added X86vzmovl patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 08:38:02 +00:00
Craig Topper
18a8e10720 Remove 0 as a valid encoding for the m-mmmm field. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191732 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 07:10:28 +00:00
Craig Topper
8568510d46 Remove unneeded fields from disassembler internal instruction format. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191731 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 06:56:57 +00:00
Craig Topper
f99f63db79 BEXTR should be defined to take same type for bother operands. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191728 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 03:48:26 +00:00
Preston Gurd
7813a2fe9d Forgot to add a break statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191715 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 23:51:22 +00:00
Preston Gurd
2967a80412 The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddress 
on ADD16rr opcodes, if src1 != src, since that would cause 
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.

This patch fixes PR16785.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191711 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 23:18:42 +00:00
Jack Carter
bdf8015cff [mips][msa] Direct Object Emission for I8 instructions. 
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191688 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 18:05:18 +00:00
Jack Carter
b0247157c6 [mips][msa] Direct Object Emission for I5 instructions. 
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191687 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-30 17:58:07 +00:00