Commit Graph

178 Commits

Author SHA1 Message Date
22f779d1fd Implememting named register intrinsics
This patch implements the infrastructure to use named register constructs in
programs that need access to specific registers (bare metal, kernels, etc).

So far, only the stack pointer is supported as a technology preview, but as it
is, the intrinsic can already support all non-allocatable registers from any
architecture.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208104 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-06 16:51:25 +00:00
a440b0f2dd Convert SelectionDAGISel::MorphNode to use ArrayRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207379 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-27 19:21:20 +00:00
d659d34219 [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203339 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-08 06:31:39 +00:00
3211c86b96 Add CheckChildInteger to ISelMatcher operations. Removes nearly 2000 bytes from X86 matcher table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-05 05:44:28 +00:00
efbb39740c [TLI] Add a new hook to TargetLowering to query the target if a load of a constant should be converted to simply the constant itself.
Before this patch we used getIntImmCost from TargetTransformInfo to determine if
a load of a constant should be converted to just a constant, but the threshold
for this was set to an arbitrary value. This value works well for the two
targets (X86 and ARM) that implement this target-hook, but it isn't
target-independent at all.

Now targets have the possibility to decide directly if this optimization should
be performed. The default value is set to false to preserve the current
behavior. The target hook has been moved to TargetLowering, which removed the
last use and need of TargetTransformInfo in SelectionDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200271 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-28 01:20:14 +00:00
936910d929 Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-05 05:38:16 +00:00
596cfd045f Revert r191940 to see if it fixes the build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191941 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 05:52:17 +00:00
d356295678 Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-04 05:22:20 +00:00
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-19 21:36:55 +00:00
6a2e7ac0b6 Cache the TargetLowering info object as a pointer.
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 00:43:09 +00:00
75299e3a95 Move TryToFoldFastISelLoad to FastISel, where it belongs. In general, I'm
trying to move as much FastISel logic as possible out of the main path in
SelectionDAGISel - intermixing them just adds confusion.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179902 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19 22:29:18 +00:00
6437d38a0d A small refactoring + adding comments.
SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it
makes sense to pass it the function instead of extracting a basic-block from
the function and then tossing it. This is also more self-documenting (functions
have arguments, BBs don't).

In addition, added comments to a couple of Select* methods.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176305 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-28 23:09:18 +00:00
674be02d52 Fix include guards so they exactly match file names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-10 00:45:19 +00:00
e4b4edd72a Funnel the actual TargetTransformInfo pass from the SelectionDAGISel
pass into the SelectionDAG itself rather than snooping on the
implementation of that pass as exposed by the TargetMachine. This
removes the last direct client of the ScalarTargetTransformInfo class
outside of the TTI pass implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-05 12:32:17 +00:00
0b8c9a80f2 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02 11:36:10 +00:00
255f89faee Sort the #include lines for the include/... tree with the script.
AKA: Recompile *ALL* the source code!

This one went much better. No manual edits here. I spot-checked for
silliness and grep-checked for really broken edits and everything seemed
good. It all still compiles. Yell if you see something that looks goofy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169133 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03 17:02:12 +00:00
8c48e4ff89 Make ISelPosition a local variable.
Now that multiple DAGUpdateListeners can be active at the same time,
ISelPosition can become a local variable in DoInstructionSelection.

We simply register an ISelUpdater with CurDAG while ISelPosition exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155249 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 22:08:50 +00:00
bc7d448f24 Register DAGUpdateListeners with SelectionDAG.
Instead of passing listener pointers to RAUW, let SelectionDAG itself
keep a linked list of interested listeners.

This makes it possible to have multiple listeners active at once, like
RAUWUpdateListener was already doing. It also makes it possible to
register listeners up the call stack without controlling all RAUW calls
below.

DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG
list of active listeners.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20 22:08:46 +00:00
50bee42b54 Convert assert(0) to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-05 22:14:15 +00:00
2d24e2a396 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 02:50:00 +00:00
243eb9ecbb Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146193 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-08 22:15:21 +00:00
29074ccf6c Remove the SystemZ backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:48:32 +00:00
b686af053e Recommit the fix for rdar://9289512 with a couple tweaks to
fix bugs exposed by the gcc dejagnu testsuite:
1. The load may actually be used by a dead instruction, which
   would cause an assert.
2. The load may not be used by the current chain of instructions,
   and we could move it past a side-effecting instruction. Change
   how we process uses to define the problem away.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 21:59:37 +00:00
63c21deee1 Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",
which broke a couple GCC test suite tests at -O0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129914 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21 16:14:46 +00:00
fd3f635103 Fix rdar://9289512 - not folding load into compare at -O0
The basic issue here is that bottom-up isel is matching the branch
and compare, and was failing to fold the load into the branch/compare
combo.  Fixing this (by allowing folding into any instruction of a
sequence that is selected) allows us to produce things like:


cmpb    $0, 52(%rax)
je      LBB4_2

instead of:

movb    52(%rax), %cl
cmpb    $0, %cl
je      LBB4_2

This makes the generated -O0 code run a bit faster, but also speeds up
compile time by putting less pressure on the register allocator and 
generating less code.

This was one of the biggest classes of missing load folding.  Implementing
this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm)
line count.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17 06:35:44 +00:00
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 05:18:47 +00:00
2d76c84514 Generalize the register matching code in DAGISel a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-01 01:37:19 +00:00
2da8bc8a5f Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
6e8f4c4048 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 04:28:06 +00:00
29d8f0cae4 flags -> glue for selectiondag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 17:24:32 +00:00
a4359be032 sdisel flag -> glue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23 17:13:18 +00:00
df8370bd70 Simplify.
Do not count use of sdisel for single call instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117316 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 21:31:46 +00:00
9c11be222c Update SelectBasicBlock signature. This should have been committed with r117310.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-25 21:04:12 +00:00
ddf897af78 tweak comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116192 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 05:48:00 +00:00
d847bc20b8 Rework passing parent pointers into complexpatterns, I forgot
that complex patterns are matched after the entire pattern has
a structural match, therefore the NodeStack isn't in a useful
state when the actual call to the matcher happens.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:00:25 +00:00
78d3af47f5 just like they can opt into getting the root of the pattern being
matched, allow ComplexPatterns to opt into getting the parent node
of the operand being matched.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114472 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:37:12 +00:00
beac75da37 implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-05 02:18:34 +00:00
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 09:00:22 +00:00
02266e29f9 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 16:37:18 +00:00
bf87e24917 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:39:23 +00:00
f595141525 Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 01:00:56 +00:00
eabaed26c3 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 16:47:08 +00:00
c9af33c685 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
SelectBasicBlock doesn't needs its BasicBlock argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06 22:19:37 +00:00
4e39e9da0f Reapply r106634, now that the bug it exposed is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 14:30:44 +00:00
cbe762b5d1 Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 17:09:26 +00:00
8a7f7426ee Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:05:21 +00:00
f81eca0ab9 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
and into SelectionDAGBuilder and FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22 20:46:50 +00:00
f0757b0edc Add more const qualifiers on TargetMachine and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21 01:34:56 +00:00
a9a3321938 Reapply the removal of SelectionDAGISel's BB, with a fix for the case
where multiple blocks are emitted; functions which do this need to return
the new BB so that their callers can stay current.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101843 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 00:29:35 +00:00
68b7960c1a Revert 101825, which is causing trouble.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101832 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19 23:34:15 +00:00