Commit Graph

18576 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
d381a7a91e Add AVX suport for fpextend.
Original patch by Syoyo Fujita with more comments by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 07:03:21 +00:00
Chad Rosier
689edc8b28 Revision r128665 added an optimization to make use of NEON multiplier
accumulator forwarding.  Specifically (from SVN log entry):

Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 01:21:54 +00:00
Bruno Cardoso Lopes
e0b5cfcae8 Silence warnings in non assert builds. Patch by David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133118 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16 00:40:02 +00:00
Jakob Stoklund Olesen
f28987b76e Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 23:28:14 +00:00
John McCall
3a3465b71d Add a new function attribute, nonlazybind, which inhibits lazy-loading
optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133080 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 20:36:13 +00:00
Jakob Stoklund Olesen
b79e30cc9e Remove custom allocation orders in SystemZ.
Note that this actually changes code generation, and someone who
understands this target better should check the changes.

- R12Q is now allocatable. I think it was omitted from the allocation
  order by mistake since it isn't reserved. It as apparently used as a
  GOT pointer sometimes, and it should probably be reserved if that is
  the case.

- The GR64 registers are allocated in a different order now. The
  register allocator will automatically put the CSRs last. There were
  other changes to the order that may have been significant.

The test fix is because r0 and r1 swapped places in the allocation order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 18:02:56 +00:00
Evan Cheng
f60ceac9cd Another revsh pattern. rdar://9609059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 17:17:48 +00:00
Roman Divacky
e355b80194 Make PPC64CompilationCallback compilable no non-darwin platforms.
Patch by Nathan Whitehorn!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 15:29:47 +00:00
Owen Anderson
1e56a2a85f Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.
At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries.  Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time.  It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133051 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 06:53:50 +00:00
Bob Wilson
7a10ab7d6f A minor simplification: no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 06:04:34 +00:00
Evan Cheng
bf188aeae7 PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
the bits being cleared by the AND are not demanded by the BFI.

The previous BFI dag combine rule was actually incorrect (or used to be
correct until BFI representation changed).

rdar://9609030


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 01:12:31 +00:00
Tanya Lattner
189531f317 Add an optimization that looks for a specific pair-wise add pattern and generates a vpaddl instruction instead of scalarizing the add.
Includes a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 23:48:48 +00:00
Anna Zaks
8d10f6d77b Anna's test commit (#2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133023 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 22:40:29 +00:00
Eli Friedman
4e3adfde65 PR10136: fix PPCTargetLowering::LowerCall_SVR4 so that a necessary CopyToReg doesn't appear to be dead.
Roman, since you're writing tests for other PPC-SVR4 vararg-related stuff, would you mind writing a test for this?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133018 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 22:16:20 +00:00
Anna Zaks
7bc5632218 Anna's test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 22:10:12 +00:00
Evan Cheng
a6eb2562b6 Also recognize ARM v4t and v5e variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133002 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 18:08:33 +00:00
Bruno Cardoso Lopes
9a767330f5 Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 04:58:37 +00:00
Nick Lewycky
3c2f0a11cc Fit banner in 80-col and adjust whitespace. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132964 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 03:23:52 +00:00
Jim Grosbach
f921c0fe34 Clean up a few 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132946 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-13 22:54:22 +00:00
Jim Grosbach
7980f61f5f Fix coordination for using R4 in Thumb1 as a scratch for SP restore.
The logic for reserving R4 for use as a scratch needs to match that for
actually using it. Also, it's not necessary for immediate <=508, so adjust
the value checked.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132934 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-13 21:18:25 +00:00
Benjamin Kramer
e7fdcad2f2 InstCombine: Fold A-b == C --> b == A-C if A and C are constants.
The backend already knew this trick.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132915 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-13 15:24:24 +00:00
Rafael Espindola
4509ec42b8 AnalyzeBranch doesn't change which successors a bb has, just the order
we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132882 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 03:20:32 +00:00
Charles Davis
aff232a594 Put FrameSetup flag on x86 instructions that set up the call frame. No
functionality change.

Later on, we'll use the flag to emit SEH pseudo-ops that describe how the
call frame was built.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132880 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12 01:45:54 +00:00
Eli Friedman
8a37aba693 Make sure to pass OpFlags into MachineInstrBuilder::addExternalSymbol; the
memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise.
Should fix llvm-x86_64-linux-checks buildbot.  Followup to r132864.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132869 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-11 01:55:07 +00:00
Eli Friedman
25255cbe00 Add full x86 fast-isel support for memcpy and memset.
rdar://9431466



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10 23:39:36 +00:00
Cameron Zwarich
a86686e643 Provide an ARMCCState subclass of CCState so that ARM clients will always set
CallOrPrologue correctly and eliminate the existing setter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10 20:59:24 +00:00
Eli Friedman
be5cbaa627 PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-10 01:13:01 +00:00
Eli Friedman
6ad0468149 Chris fixed this README a while back by changing how clang generates code for structs like the given struct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132815 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 23:02:19 +00:00
Cameron Zwarich
a2e979565b A CCState was being created without setting whether it is in the Call or Prologue state,
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 22:30:07 +00:00
Roman Divacky
a1000742d2 Fix emission of PPC64 assembler on non-darwin platforms by splitting
VK_PPC_{HA,LO}16 into darwin and gas variants.

Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132802 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 20:25:38 +00:00
Eli Friedman
6f19c67d84 Revert 132789; it breaks tests. My mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 19:33:30 +00:00
Eli Friedman
aebc3c1610 Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132789 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 18:55:00 +00:00
Jakob Stoklund Olesen
2a9d1ca9c2 Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 16:56:59 +00:00
Eric Christopher
6f3661fdcd Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 16:03:19 +00:00
Duncan Sands
9fe88973be Enable printf() to iprintf() optimization for the TCE target.
Patch by Pekka Jaaskelainen. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132774 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 11:11:45 +00:00
Akira Hatanaka
c53cc48ca9 Initial support for inline asm memory operand constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132768 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09 03:31:05 +00:00
Eric Christopher
471e422480 Add a parameter to CCState so that it can access the MachineFunction.
No functional change.

Part of PR6965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08 23:55:35 +00:00
Akira Hatanaka
69b9044c66 Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
dynamically allocated stack area was not set.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08 21:28:09 +00:00
Akira Hatanaka
3d21c2495d Reorganize code in MipsTargetLowering::LowerCall to improve readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08 17:39:33 +00:00
Akira Hatanaka
14487d4f66 Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132726 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 19:28:39 +00:00
Akira Hatanaka
c079ad09f5 Put back removed line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132725 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 19:03:14 +00:00
Akira Hatanaka
0f84382138 Coding style fixes.
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132724 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 18:58:42 +00:00
Akira Hatanaka
ffe9a7116c Use tabs to separate opcode and operand strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 18:16:51 +00:00
Akira Hatanaka
6cd4b4e657 Add comments for wrapper node patterns in MipsInstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132717 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 18:00:14 +00:00
Akira Hatanaka
8464fff30b Add test case for C++ exception handling and fix the following mistakes in MipsFrameLowering::emitPrologue:
- cfi directives are not inserted at the right location or in the right order.
- The source MachineLocation for the cfi directive that changes the cfa register
  to $fp should be MachineLocation::VirtualFP.
- A PROLOG_LABEL that marks the beginning of cfi_offset directives for
  callee-saved register is emitted even when no callee-saved registers are
  saved.
- When a callee-saved double precision register is saved, two cfi_offset
  directives, one for each of the paired single precision registers, should be
  emitted.
 
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132703 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 02:17:21 +00:00
Andrew Trick
a1099f184d Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.
rdar://problem/9556069


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132699 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 00:08:49 +00:00
Stuart Hastings
f99a4b82a4 Followup to 132458, omit unnecessary stack copy when x87 input is a
load.  rdar://problem/6373334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-06 23:15:58 +00:00
Stuart Hastings
865f09334f Reapply 132424 with fixes. This fixes PR10068.
rdar://problem/5993888


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 23:53:54 +00:00
Jakob Stoklund Olesen
7b5fdc7fbd Blackfin always uses a reserved call frame.
Materializing the stack pointer update before a call requires a scratch
register that may not be available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132601 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 22:45:18 +00:00
Eric Christopher
cf714d44b8 Make the Uv constraint a memory operand. This doesn't solve the
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03 17:24:37 +00:00