about whether the new base ptr would be live below the load/store. Let two
address pass split it back to non-indexed ops.
- Minor tweaks / fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31544 91177308-0d34-0410-b5e6-96231b3b80d8
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31542 91177308-0d34-0410-b5e6-96231b3b80d8
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
jne LBB1_57 #bb207.i
jmp LBB1_64 #cond_next255.i
intead of:
LBB1_57: #bb207.i
movl 72(%esp), %ecx
movb (%ecx,%eax), %cl
movl 80(%esp), %edx
movb %cl, 1(%edx,%eax)
incl %eax
cmpl $143, %eax
je LBB1_64 #cond_next255.i
jmp LBB1_57 #bb207.i
This eliminates a branch per iteration of the loop. This hurted PPC
particularly, because the extra branch meant another dispatch group for each
iteration of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31530 91177308-0d34-0410-b5e6-96231b3b80d8
empty ranges.
2. Reorg how MachineDebugInfo maintains changes to debug labels.
3. Have dwarf writer use debug label info to simplify scopes and source line
coorespondence.
4. Revert the merging of compile units until I can get the bugs ironed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31507 91177308-0d34-0410-b5e6-96231b3b80d8
by 40%, FreeBench/fourinarow by 20%, and many other programs 10-25%.
On PPC, this speeds up fourinarow by 18%, and probably other things as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31504 91177308-0d34-0410-b5e6-96231b3b80d8
NOTE: There doesn't seem to be consistency for whether a leading tab
is present in a section heading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31475 91177308-0d34-0410-b5e6-96231b3b80d8
there may be other def(s) apart from the use&def two-address operand. We need
to check if the register reuse for a use&def operand may conflicts with another
def. Provide a mean to recover from the conflict if it is detected when the
defs are processed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31439 91177308-0d34-0410-b5e6-96231b3b80d8
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
1. Most significant is the folding of debug information entries. This
reduced self hosted -g SelectionDAGISel.s from 120M to 13M and pretty
close to matching .o file sizes with gcc.
2. Debug information entry printing for debugging the dwarf code.
3. Bring all the code closer to llvm standards.
4. Misc. fixes and doc clean ups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31379 91177308-0d34-0410-b5e6-96231b3b80d8
no fixes physreg. Treat this as permission to use any register in the register
class. When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time. This eliminates a ton
of copies around common inline asms. For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31366 91177308-0d34-0410-b5e6-96231b3b80d8
it inserts an uncond branch where it is less likely to cause a problem. This
fixes some perf issues on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31354 91177308-0d34-0410-b5e6-96231b3b80d8
