Evan Cheng
046fa3f90a
Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:26:21 +00:00
Dale Johannesen
4a12de72b0
Make g5 target explicit; scheduling affects register choice.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96413 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 23:25:23 +00:00
Dale Johannesen
55f9adf543
Adjust register numbers in tests to compensate for the
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new lack of R2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96407 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-16 22:31:31 +00:00
Dan Gohman
fce288fc91
Eliminate more uses of llvm-as and llvm-dis.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
Dale Johannesen
4e68f8803d
Alter 79292 to produce output that actually assembles.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80119 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-26 18:10:32 +00:00
Dale Johannesen
5cfd4ddece
PowerPC inline asm was emitting two output operands
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for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible. 7144566.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-18 00:18:39 +00:00
