Commit Graph

238 Commits

Author SHA1 Message Date
Evan Cheng
28c85a81a1 Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26 00:42:34 +00:00
Evan Cheng
78c10eeaa5 Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25 23:24:55 +00:00
Evan Cheng
203576aa0c Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 19:50:42 +00:00
Evan Cheng
34ad6db8b9 - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 07:51:56 +00:00
Evan Cheng
e76a33b956 Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20 05:58:47 +00:00
Evan Cheng
439661395f Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19 06:37:02 +00:00
Evan Cheng
0e6a052331 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18 20:57:22 +00:00
Evan Cheng
1abf2cb59b Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14 23:50:31 +00:00
Evan Cheng
59ee62d241 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11 03:57:24 +00:00
Evan Cheng
ebdeeab812 Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08 01:53:10 +00:00
Evan Cheng
b262799d49 createMCInstPrinter doesn't need TargetMachine anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134525 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-06 19:45:42 +00:00
Dan Gohman
9c04b5bd28 Remove the ObjC ARC passes from the default optimization list, and add
extension points to be used by clang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-05 22:01:44 +00:00
Rafael Espindola
2548391104 Move early tail duplication earlier.
This fixes the issue noted in PR10251 where early tail dup of bbs with
indirectbr would cause a bb to be duplicated into a loop preheader
and then into its predecessors, creating phi nodes with identical
operands just before register allocation.

This helps with jsinterp.o size (__TEXT goes from 163568 to 126656)
and a bit with performance 1.005x faster on sunspider (jits still enabled).

The result on webkit with the jit disabled is more significant: 1.021x faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134372 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-04 04:54:22 +00:00
Bill Wendling
e266ce6c6e Use the verbose asm flag instead of a new flag for decoding the LSDA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17 20:55:01 +00:00
Bill Wendling
916a94b870 Add an option that allows one to "decode" the LSDA.
The LSDA is a bit difficult for the non-initiated to read. Even with comments,
it's not always clear what's going on. This wraps the ASM streamer in a class
that retains the LSDA and then emits a human-readable description of what's
going on in it.

So instead of having to make sense of:

Lexception1:
        .byte   255
        .byte   155
        .byte   168
        .space  1
        .byte   3
        .byte   26
Lset0 = Ltmp7-Leh_func_begin1
      .long     Lset0
Lset1 = Ltmp812-Ltmp7
      .long     Lset1
Lset2 = Ltmp913-Leh_func_begin1
      .long     Lset2
      .byte     3
Lset3 = Ltmp812-Leh_func_begin1
      .long     Lset3
Lset4 = Leh_func_end1-Ltmp812
      .long     Lset4
      .long     0
      .byte     0
      .byte     1
      .byte     0
      .byte     2
      .byte     125
      .long     __ZTIi@GOTPCREL+4
      .long     __ZTIPKc@GOTPCREL+4

you can read this instead:

## Exception Handling Table: Lexception1
##  @LPStart Encoding: omit
##    @TType Encoding: indirect pcrel sdata4
##        @TType Base: 40 bytes
## @CallSite Encoding: udata4
## @Action Table Size: 26 bytes

## Action 1:
##   A throw between Ltmp7 and Ltmp812 jumps to Ltmp913 on an exception.
##     For type(s):  __ZTIi@GOTPCREL+4 __ZTIPKc@GOTPCREL+4
## Action 2:
##   A throw between Ltmp812 and Leh_func_end1 does not have a landing pad.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133286 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17 20:35:21 +00:00
John McCall
9fbd318d36 The ARC language-specific optimizer. Credit to Dan Gohman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133108 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 23:37:01 +00:00
Charles Davis
d652b1368b Stub out support for Win64-style exceptions. Note that this is merely using
the Win64 EH mechanism to implement GCC-style exceptions. LLVM supports
hardly anything else at this point!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132234 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:47:32 +00:00
Chris Lattner
402d9d9935 eliminate dependence on StandardPasses.h. The code generator's pass pipeline
should eventually convert to PMBuilder, but I don't plan to do this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131819 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 00:13:44 +00:00
Rafael Espindola
254784f9e0 Remove the DwarfTable enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05 22:14:31 +00:00
Rafael Espindola
f1a5c7ec04 Add all the plumbing needed for MC to expand cfi to the old tables in
the final assembly. It is the same technique used when targeting
assemblers that don't support .loc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-30 03:44:37 +00:00
Daniel Dunbar
a7b8c2b6a4 Integrated-As: Add support for setting the AllowTemporaryLabels flag via
integrated-as.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28 22:49:19 +00:00
Bill Wendling
a5c177e70a We need to pass the TargetMachine object to the InstPrinter if we are printing
the alias of an InstAlias instead of the thing being aliased. Because we need to
know the features that are valid for an InstAlias.

This is part of a work-in-progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 04:13:46 +00:00
Jim Grosbach
31649e61bc Beginnings of MC-JIT code generation.
Proof-of-concept code that code-gens a module to an in-memory MachO object.
This will be hooked up to a run-time dynamic linker library (see: llvm-rtdyld
for similarly conceptual work for that part) which will take the compiled
object and link it together with the rest of the system, providing back to the
JIT a table of available symbols which will be used to respond to the
getPointerTo*() queries.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 22:48:41 +00:00
Anton Korobeynikov
b5e16af9ea Some first rudimentary support for ARM EHABI: print exception table in "text mode".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127099 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05 18:43:15 +00:00
Dan Gohman
00141694fa Delete the GEPSplitter experiment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126671 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 19:47:47 +00:00
Rafael Espindola
96aa78c8c5 Add support for the --noexecstack option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23 17:55:27 +00:00
Anton Korobeynikov
3965b5e974 Add a possibility to switch between CFI directives- and table-based frame description emission. Currently all the backends use table-based stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-14 21:58:08 +00:00
Jakob Stoklund Olesen
89cab93fe9 Pass a Banner argument to the machine code verifier both from
createMachineVerifierPass and MachineFunction::verify.

The banner is printed before the machine code dump, just like the printer pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122113 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18 00:06:56 +00:00
Daniel Dunbar
745dacc91d MC: Make TargetAsmBackend available to the AsmStreamer.
- Treaty talks on the non-proliferation of MC objects broke down.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16 03:05:59 +00:00
Rafael Espindola
89b9372605 Fixed version of 121434 with no new memory leaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 07:39:47 +00:00
Rafael Espindola
f7fd4aa261 Revert my previous patch to make the valgrind bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10 04:01:09 +00:00
Rafael Espindola
1c952b9cc9 Initial support for the cfi directives. This is just enough to get
f:
        .cfi_startproc
        nop
        .cfi_endproc

assembled (on ELF).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09 23:48:29 +00:00
Rafael Espindola
195a0ce484 Change some methods in MCDwarf.cpp to be able to handle an arbitrary
MCStreamer instead of just MCObjectStreamer. Address changes cannot
be as efficient as we have to use DW_LNE_set_addres, but at least
most of the logic is shared.

This will be used so that, with CodeGen still using EmitDwarfLocDirective,
llvm-gcc is able to produce debug_line sections without needing an
assembler that supports .loc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119777 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19 02:26:16 +00:00
Dan Gohman
bd77d399c4 Oops, missed this file when remaing ExpandPseudos to ExpandISelPseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18 18:48:28 +00:00
Evan Cheng
c4af4638df Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 20:13:28 +00:00
Dan Gohman
668ac2fdae Split pseudo-instruction expansion into a separate pass, to make it
easier to debug, and to avoid complications when the CFG changes
in the middle of the instruction selection process.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-16 21:02:37 +00:00
Che-Liang Chiou
6da24ca51d Add registry hook for assembly text output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08 02:21:17 +00:00
Dan Gohman
4021fccf9f Add TypeBasedAliasAnalysis to the standard pass lists. Note that it
is currently inert by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116732 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:50:27 +00:00
Dan Gohman
c1be92f3bb Make BasicAliasAnalysis a normal AliasAnalysis implementation which
does normal initialization and normal chaining. Change the default
AliasAnalysis implementation to NoAlias.

Update StandardCompileOpts.h and friends to explicitly request
BasicAliasAnalysis.

Update tests to explicitly request -basicaa.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 18:04:47 +00:00
Rafael Espindola
ff9dfedd10 Call InitSections in llc and clang so that the binaries produced by them
are easier to diff with those produced by llvm-mc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 19:37:38 +00:00
Duncan Sands
22efc18f12 Stop using the dom frontier in DwarfEHPrepare by not promoting alloca's
any more.  I plan to reimplement alloca promotion using SSAUpdater later.
It looks like Bill's URoR logic really always needs domtree, so the pass
now always asks for domtree info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-31 09:05:06 +00:00
Jim Grosbach
a273442891 Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24 19:05:43 +00:00
Jim Grosbach
3d72367d30 Add a local stack object block allocation pass. This is still an
experimental pass that allocates locals relative to one another before
register allocation and then assigns them to actual stack slots as a block
later in PEI. This will eventually allow targets with limited index offset
range to allocate additional base registers (not just FP and SP) to
more efficiently reference locals, as well as handle situations where
locals cannot be referenced via SP or FP at all (dynamic stack realignment
together with variable sized objects, for example). It's currently
incomplete and almost certainly buggy. Work in progress.

Disabled by default and gated via the -enable-local-stack-alloc command
line option.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14 00:15:52 +00:00
Jim Grosbach
c92bb50a0c tidy up whitespace a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111019 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13 16:55:08 +00:00
Bill Wendling
6cdb1abe4e Merge the OptimizeExts and OptimizeCmps passes into one PeepholeOptimizer
pass. This pass should expand with all of the small, fine-grained optimization
passes to reduce compile time and increase happiment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110627 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 23:59:04 +00:00
Bill Wendling
e4ddbdfd3c Add the Optimize Compares pass (disabled by default).
This pass tries to remove comparison instructions when possible. For instance,
if you have this code:

   sub r1, 1
   cmp r1, 0
   bz  L1

and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06 01:32:48 +00:00
Jakob Stoklund Olesen
73cf709a08 Remove double-def checking from MachineVerifier, so a register does not have to
be killed before being redefined.

These checks are usually disabled, and usually fail when enabled. We de facto
allow live registers to be redefined without a kill, the corresponding
assertions in RegScavenger were removed long ago.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110362 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 18:59:59 +00:00
Bill Wendling
af33b7b4a7 The lower invoke pass needs to have unreachable code elimination run after it
because it could create such things. This fixes a MingW buildbot test failure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 23:36:02 +00:00
Bill Wendling
2464d618c0 The EH prepare passes really want to be the last passes run before code-gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 21:44:13 +00:00
Benjamin Kramer
1abcd06856 Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ownership of the TargetAsmBackend and the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 17:48:06 +00:00