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Introduce MCCodeGenInfo, which keeps information that can affect codegen

Browse Source 
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-07-19 06:37:02 +00:00
parent 939ece1b5c
commit 439661395f
74 changed files with 641 additions and 314 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
autoconf/configure.ac
View File

@ -659,6 +659,7 @@ for a_target in $TARGETS_TO_BUILD; do
LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target"
LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo"
LLVM_NATIVE_MCASMINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo"
LLVM_NATIVE_MCCODEGENINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo"
LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter"
if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then
LLVM_NATIVE_ASMPARSER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser"
@ -669,6 +670,8 @@ for a_target in $TARGETS_TO_BUILD; do
[LLVM name for the native TargetInfo init function, if available])
AC_DEFINE_UNQUOTED(LLVM_NATIVE_MCASMINFO, $LLVM_NATIVE_MCASMINFO,
[LLVM name for the native MCAsmInfo init function, if available])
AC_DEFINE_UNQUOTED(LLVM_NATIVE_MCCODEGENINFO, $LLVM_NATIVE_MCCODEGENINFO,
[LLVM name for the native MCCodeGenInfo init function, if available])
AC_DEFINE_UNQUOTED(LLVM_NATIVE_ASMPRINTER, $LLVM_NATIVE_ASMPRINTER,
[LLVM name for the native AsmPrinter init function, if available])
if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then

1
cmake/config-ix.cmake
View File

@ -337,6 +337,7 @@ else ()
set(LLVM_NATIVE_TARGET LLVMInitialize${LLVM_NATIVE_ARCH}Target)
set(LLVM_NATIVE_TARGETINFO LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo)
set(LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo)
set(LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCODEGENInfo)
set(LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter)
endif ()

6
configure vendored
View File

@ -5121,6 +5121,7 @@ _ACEOF
LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target"
LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo"
LLVM_NATIVE_MCASMINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo"
LLVM_NATIVE_MCCODEGENINFO="LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo"
LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter"
if test -f ${srcdir}/lib/Target/${LLVM_NATIVE_ARCH}/AsmParser/Makefile ; then
LLVM_NATIVE_ASMPARSER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser"
@ -5141,6 +5142,11 @@ cat >>confdefs.h <<_ACEOF
_ACEOF
cat >>confdefs.h <<_ACEOF
#define LLVM_NATIVE_MCCODEGENINFO $LLVM_NATIVE_MCCODEGENINFO
_ACEOF
cat >>confdefs.h <<_ACEOF
#define LLVM_NATIVE_ASMPRINTER $LLVM_NATIVE_ASMPRINTER
_ACEOF

6
include/llvm-c/Target.h
View File

@ -46,6 +46,11 @@ typedef struct LLVMStructLayout *LLVMStructLayoutRef;
#include "llvm/Config/Targets.def"
#undef LLVM_TARGET /* Explicit undef to make SWIG happier */
#define LLVM_TARGET(TargetName) \
void LLVMInitialize##TargetName##MCCodeGenInfo(void);
#include "llvm/Config/Targets.def"
#undef LLVM_TARGET /* Explicit undef to make SWIG happier */
/** LLVMInitializeAllTargetInfos - The main program should call this function if
it wants access to all available targets that LLVM is configured to
support. */
@ -73,6 +78,7 @@ static inline LLVMBool LLVMInitializeNativeTarget(void) {
LLVM_NATIVE_TARGETINFO();
LLVM_NATIVE_TARGET();
LLVM_NATIVE_MCASMINFO();
LLVM_NATIVE_MCCODEGENINFO();
return 0;
#else
return 1;

3
include/llvm/Config/config.h.cmake
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@ -560,6 +560,9 @@
/* LLVM name for the native MCAsmInfo init function, if available */
#cmakedefine LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo
/* LLVM name for the native MCCodeGenInfo init function, if available */
#cmakedefine LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo
/* Define if this is Unixish platform */
#cmakedefine LLVM_ON_UNIX ${LLVM_ON_UNIX}

3
include/llvm/Config/config.h.in
View File

@ -576,6 +576,9 @@
/* LLVM name for the native MCAsmInfo init function, if available */
#undef LLVM_NATIVE_MCASMINFO
/* LLVM name for the native MCCODEGENInfo init function, if available */
#undef LLVM_NATIVE_MCCODEGENINFO
/* LLVM name for the native Target init function, if available */
#undef LLVM_NATIVE_TARGET

3
include/llvm/Config/llvm-config.h.cmake
View File

@ -61,6 +61,9 @@
/* LLVM name for the native MCAsmInfo init function, if available */
#cmakedefine LLVM_NATIVE_MCASMINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCAsmInfo
/* LLVM name for the native MCCodeGenInfo init function, if available */
#cmakedefine LLVM_NATIVE_MCCODEGENINFO LLVMInitialize${LLVM_NATIVE_ARCH}MCCodeGenInfo
/* LLVM name for the native AsmPrinter init function, if available */
#cmakedefine LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter

3
include/llvm/Config/llvm-config.h.in
View File

@ -61,6 +61,9 @@
/* LLVM name for the native MCAsmInfo init function, if available */
#undef LLVM_NATIVE_MCASMINFO
/* LLVM name for the native MCCodeGenInfo init function, if available */
#undef LLVM_NATIVE_MCCODEGENINFO
/* LLVM name for the native AsmPrinter init function, if available */
#undef LLVM_NATIVE_ASMPRINTER

12
include/llvm/ExecutionEngine/ExecutionEngine.h
View File

@ -18,6 +18,7 @@
#include <vector>
#include <map>
#include <string>
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/ValueMap.h"
@ -201,6 +202,7 @@ public:
CodeGenOpt::Level OptLevel =
CodeGenOpt::Default,
bool GVsWithCode = true,
Reloc::Model RM = Reloc::Default,
CodeModel::Model CMM =
CodeModel::Default);
@ -463,6 +465,7 @@ private:
CodeGenOpt::Level OptLevel;
JITMemoryManager *JMM;
bool AllocateGVsWithCode;
Reloc::Model RelocModel;
CodeModel::Model CMModel;
std::string MArch;
std::string MCPU;
@ -476,6 +479,7 @@ private:
OptLevel = CodeGenOpt::Default;
JMM = NULL;
AllocateGVsWithCode = false;
RelocModel = Reloc::Default;
CMModel = CodeModel::Default;
UseMCJIT = false;
}
@ -517,6 +521,13 @@ public:
return *this;
}
/// setRelocationModel - Set the relocation model that the ExecutionEngine
/// target is using. Defaults to target specific default "Reloc::Default".
EngineBuilder &setRelocationModel(Reloc::Model RM) {
RelocModel = RM;
return *this;
}
/// setCodeModel - Set the CodeModel that the ExecutionEngine target
/// data is using. Defaults to target specific default "CodeModel::Default".
EngineBuilder &setCodeModel(CodeModel::Model M) {
@ -569,6 +580,7 @@ public:
StringRef MArch,
StringRef MCPU,
const SmallVectorImpl<std::string>& MAttrs,
Reloc::Model RM,
std::string *Err);
ExecutionEngine *create();

36
include/llvm/MC/MCCodeGenInfo.h Normal file
View File

@ -0,0 +1,36 @@
//===-- llvm/MC/MCCodeGenInfo.h - Target CodeGen Info -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file tracks information about the target which can affect codegen,
// asm parsing, and asm printing. For example, relocation model.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_MC_MCCODEGENINFO_H
#define LLVM_MC_MCCODEGENINFO_H
namespace llvm {
// Relocation model types.
namespace Reloc {
enum Model { Default, Static, PIC_, DynamicNoPIC };
}
class MCCodeGenInfo {
/// RelocationModel - Relocation model: statcic, pic, etc.
///
Reloc::Model RelocationModel;
public:
void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default);
Reloc::Model getRelocationModel() const { return RelocationModel; }
};
} // namespace llvm
#endif

24
include/llvm/Target/TargetMachine.h
View File

@ -14,6 +14,7 @@
#ifndef LLVM_TARGET_TARGETMACHINE_H
#define LLVM_TARGET_TARGETMACHINE_H
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/ADT/StringRef.h"
#include <cassert>
#include <string>
@ -23,6 +24,7 @@ namespace llvm {
class InstrItineraryData;
class JITCodeEmitter;
class MCAsmInfo;
class MCCodeGenInfo;
class MCContext;
class Pass;
class PassManager;
@ -41,16 +43,6 @@ class TargetSubtargetInfo;
class formatted_raw_ostream;
class raw_ostream;
// Relocation model types.
namespace Reloc {
enum Model {
Default,
Static,
PIC_, // Cannot be named PIC due to collision with -DPIC
DynamicNoPIC
};
}
// Code model types.
namespace CodeModel {
enum Model {
@ -108,6 +100,10 @@ protected: // Can only create subclasses.
std::string TargetCPU;
std::string TargetFS;
/// CodeGenInfo - Low level target information such as relocation model.
///
const MCCodeGenInfo *CodeGenInfo;
/// AsmInfo - Contains target specific asm information.
///
const MCAsmInfo *AsmInfo;
@ -214,11 +210,7 @@ public:
/// getRelocationModel - Returns the code generation relocation model. The
/// choices are static, PIC, and dynamic-no-pic, and target default.
static Reloc::Model getRelocationModel();
/// setRelocationModel - Sets the code generation relocation model.
///
static void setRelocationModel(Reloc::Model Model);
Reloc::Model getRelocationModel() const;
/// getCodeModel - Returns the code model. The choices are small, kernel,
/// medium, large, and target default.
@ -309,7 +301,7 @@ public:
class LLVMTargetMachine : public TargetMachine {
protected: // Can only create subclasses.
LLVMTargetMachine(const Target &T, StringRef TargetTriple,
StringRef CPU, StringRef FS);
StringRef CPU, StringRef FS, Reloc::Model RM);
private:
/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for

87
include/llvm/Target/TargetRegistry.h
View File

@ -19,6 +19,7 @@
#ifndef LLVM_TARGET_TARGETREGISTRY_H
#define LLVM_TARGET_TARGETREGISTRY_H
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/ADT/Triple.h"
#include <string>
#include <cassert>
@ -37,6 +38,7 @@ namespace llvm {
class MCRegisterInfo;
class MCStreamer;
class MCSubtargetInfo;
class MCCodeGenInfo;
class TargetAsmBackend;
class TargetAsmLexer;
class TargetAsmParser;
@ -68,15 +70,17 @@ namespace llvm {
typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
StringRef TT);
typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT, Reloc::Model M);
typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
StringRef CPU,
StringRef Features);
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &Features);
StringRef TT,
StringRef CPU,
StringRef Features,
Reloc::Model RM);
typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
MCStreamer &Streamer);
typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T,
@ -132,6 +136,10 @@ namespace llvm {
/// registered.
MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
/// MCCodeGenInfoCtorFn - Constructor function for this target's MCCodeGenInfo,
/// if registered.
MCCodeGenInfoCtorFnTy MCCodeGenInfoCtorFn;
/// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
/// if registered.
MCInstrInfoCtorFnTy MCInstrInfoCtorFn;
@ -253,6 +261,14 @@ namespace llvm {
return MCAsmInfoCtorFn(*this, Triple);
}
/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
///
MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model M) const {
if (!MCCodeGenInfoCtorFn)
return 0;
return MCCodeGenInfoCtorFn(Triple, M);
}
/// createMCInstrInfo - Create a MCInstrInfo implementation.
///
MCInstrInfo *createMCInstrInfo() const {
@ -292,12 +308,12 @@ namespace llvm {
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
TargetMachine *createTargetMachine(const std::string &Triple,
const std::string &CPU,
const std::string &Features) const {
TargetMachine *createTargetMachine(StringRef Triple, StringRef CPU,
StringRef Features,
Reloc::Model RM = Reloc::Default) const {
if (!TargetMachineCtorFn)
return 0;
return TargetMachineCtorFn(*this, Triple, CPU, Features);
return TargetMachineCtorFn(*this, Triple, CPU, Features, RM);
}
/// createAsmBackend - Create a target specific assembly parser.
@ -500,6 +516,22 @@ namespace llvm {
T.MCAsmInfoCtorFn = Fn;
}
/// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the
/// given target.
///
/// Clients are responsible for ensuring that registration doesn't occur
/// while another thread is attempting to access the registry. Typically
/// this is done by initializing all targets at program startup.
///
/// @param T - The target being registered.
/// @param Fn - A function to construct a MCCodeGenInfo for the target.
static void RegisterMCCodeGenInfo(Target &T,
Target::MCCodeGenInfoCtorFnTy Fn) {
// Ignore duplicate registration.
if (!T.MCCodeGenInfoCtorFn)
T.MCCodeGenInfoCtorFn = Fn;
}
/// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the
/// given target.
///
@ -756,6 +788,39 @@ namespace llvm {
}
};
/// RegisterMCCodeGenInfo - Helper template for registering a target codegen info
/// implementation. This invokes the static "Create" method on the class
/// to actually do the construction. Usage:
///
/// extern "C" void LLVMInitializeFooTarget() {
/// extern Target TheFooTarget;
/// RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget);
/// }
template<class MCCodeGenInfoImpl>
struct RegisterMCCodeGenInfo {
RegisterMCCodeGenInfo(Target &T) {
TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
}
private:
static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model M) {
return new MCCodeGenInfoImpl();
}
};
/// RegisterMCCodeGenInfoFn - Helper template for registering a target codegen
/// info implementation. This invokes the specified function to do the
/// construction. Usage:
///
/// extern "C" void LLVMInitializeFooTarget() {
/// extern Target TheFooTarget;
/// RegisterMCCodeGenInfoFn X(TheFooTarget, TheFunction);
/// }
struct RegisterMCCodeGenInfoFn {
RegisterMCCodeGenInfoFn(Target &T, Target::MCCodeGenInfoCtorFnTy Fn) {
TargetRegistry::RegisterMCCodeGenInfo(T, Fn);
}
};
/// RegisterMCInstrInfo - Helper template for registering a target instruction
/// info implementation. This invokes the static "Create" method on the class
/// to actually do the construction. Usage:
@ -871,10 +936,10 @@ namespace llvm {
}
private:
static TargetMachine *Allocator(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS) {
return new TargetMachineImpl(T, TT, CPU, FS);
static TargetMachine *Allocator(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM) {
return new TargetMachineImpl(T, TT, CPU, FS, RM);
}
};

15
include/llvm/Target/TargetSelect.h
View File

@ -30,6 +30,10 @@ extern "C" {
void LLVMInitialize##TargetName##MCAsmInfo();
#include "llvm/Config/Targets.def"
#define LLVM_TARGET(TargetName) \
void LLVMInitialize##TargetName##MCCodeGenInfo();
#include "llvm/Config/Targets.def"
#define LLVM_TARGET(TargetName) \
void LLVMInitialize##TargetName##MCInstrInfo();
#include "llvm/Config/Targets.def"
@ -91,6 +95,16 @@ namespace llvm {
#include "llvm/Config/Targets.def"
}
/// InitializeAllMCCodeGenInfos - The main program should call this function
/// if it wants access to all targets machines that LLVM is configured to
/// support, to make them available via the TargetRegistry.
///
/// It is legal for a client to make multiple calls to this function.
inline void InitializeAllMCCodeGenInfos() {
#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCCodeGenInfo();
#include "llvm/Config/Targets.def"
}
/// InitializeAllMCInstrInfos - The main program should call this function
/// if it wants access to all available instruction infos for targets that
/// LLVM is configured to support, to make them available via the
@ -164,6 +178,7 @@ namespace llvm {
LLVM_NATIVE_TARGETINFO();
LLVM_NATIVE_TARGET();
LLVM_NATIVE_MCASMINFO();
LLVM_NATIVE_MCCODEGENINFO();
return false;
#else
return true;

4
lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -103,8 +103,10 @@ EnableFastISelOption("fast-isel", cl::Hidden,
cl::desc("Enable the \"fast\" instruction selector"));
LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
StringRef CPU, StringRef FS)
StringRef CPU, StringRef FS,
Reloc::Model RM)
: TargetMachine(T, Triple, CPU, FS) {
CodeGenInfo = T.createMCCodeGenInfo(Triple, RM);
AsmInfo = T.createMCAsmInfo(Triple);
}

7
lib/ExecutionEngine/ExecutionEngine.cpp
View File

@ -422,6 +422,7 @@ ExecutionEngine *ExecutionEngine::createJIT(Module *M,
JITMemoryManager *JMM,
CodeGenOpt::Level OptLevel,
bool GVsWithCode,
Reloc::Model RM,
CodeModel::Model CMM) {
if (ExecutionEngine::JITCtor == 0) {
if (ErrorStr)
@ -436,7 +437,7 @@ ExecutionEngine *ExecutionEngine::createJIT(Module *M,
SmallVector<std::string, 1> MAttrs;
TargetMachine *TM =
EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, ErrorStr);
EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, RM, ErrorStr);
if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0;
TM->setCodeModel(CMM);
@ -465,8 +466,8 @@ ExecutionEngine *EngineBuilder::create() {
// Unless the interpreter was explicitly selected or the JIT is not linked,
// try making a JIT.
if (WhichEngine & EngineKind::JIT) {
if (TargetMachine *TM =
EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs, ErrorStr)) {
if (TargetMachine *TM = EngineBuilder::selectTarget(M, MArch, MCPU, MAttrs,
RelocModel, ErrorStr)) {
TM->setCodeModel(CMModel);
if (UseMCJIT && ExecutionEngine::MCJITCtor) {

3
lib/ExecutionEngine/JIT/JIT.h
View File

@ -100,9 +100,10 @@ public:
CodeGenOpt::Level OptLevel =
CodeGenOpt::Default,
bool GVsWithCode = true,
Reloc::Model RM = Reloc::Default,
CodeModel::Model CMM = CodeModel::Default) {
return ExecutionEngine::createJIT(M, Err, JMM, OptLevel, GVsWithCode,
CMM);
RM, CMM);
}
virtual void addModule(Module *M);

5
lib/ExecutionEngine/TargetSelect.cpp
View File

@ -30,6 +30,7 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod,
StringRef MArch,
StringRef MCPU,
const SmallVectorImpl<std::string>& MAttrs,
Reloc::Model RM,
std::string *ErrorStr) {
Triple TheTriple(Mod->getTargetTriple());
if (TheTriple.getTriple().empty())
@ -83,8 +84,8 @@ TargetMachine *EngineBuilder::selectTarget(Module *Mod,
}
// Allocate a target...
TargetMachine *Target =
TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr);
TargetMachine *Target = TheTarget->createTargetMachine(TheTriple.getTriple(),
MCPU, FeaturesStr, RM);
assert(Target && "Could not allocate target machine!");
return Target;
}

1
lib/MC/CMakeLists.txt
View File

@ -6,6 +6,7 @@ add_llvm_library(LLVMMC
MCAsmStreamer.cpp
MCAssembler.cpp
MCCodeEmitter.cpp
MCCodeGenInfo.cpp
MCContext.cpp
MCDisassembler.cpp
MCELF.cpp

20
lib/MC/MCCodeGenInfo.cpp Normal file
View File

@ -0,0 +1,20 @@
//===-- MCCodeGenInfo.cpp - Target CodeGen Info -----------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file tracks information about the target which can affect codegen,
// asm parsing, and asm printing. For example, relocation model.
//
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCCodeGenInfo.h"
using namespace llvm;
void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM) {
RelocationModel = RM;
}

1
lib/MC/MCDisassembler/Disassembler.cpp
View File

@ -41,6 +41,7 @@ LLVMDisasmContextRef LLVMCreateDisasm(const char *TripleName, void *DisInfo,
// FIXME: We shouldn't need to initialize the Target(Machine)s.
llvm::InitializeAllTargets();
llvm::InitializeAllMCAsmInfos();
llvm::InitializeAllMCCodeGenInfos();
llvm::InitializeAllMCRegisterInfos();
llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();

1
lib/MC/MCDisassembler/EDDisassembler.cpp
View File

@ -108,6 +108,7 @@ void EDDisassembler::initialize() {
InitializeAllTargetInfos();
InitializeAllTargets();
InitializeAllMCCodeGenInfos();
InitializeAllMCAsmInfos();
InitializeAllMCRegisterInfos();
InitializeAllMCSubtargetInfos();

31
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -62,25 +62,22 @@ extern "C" void LLVMInitializeARMTarget() {
/// TargetMachine ctor - Create an ARM architecture model.
///
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: LLVMTargetMachine(T, TT, CPU, FS),
ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS),
JITInfo(),
InstrItins(Subtarget.getInstrItineraryData()) {
DefRelocModel = getRelocationModel();
// Default to soft float ABI
if (FloatABIType == FloatABI::Default)
FloatABIType = FloatABI::Soft;
}
ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: ARMBaseTargetMachine(T, TT, CPU, FS), InstrInfo(Subtarget),
ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM), InstrInfo(Subtarget),
DataLayout(Subtarget.isAPCS_ABI() ?
std::string("e-p:32:32-f64:32:64-i64:32:64-"
"v128:32:128-v64:32:64-n32") :
@ -95,10 +92,10 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
"support ARM mode execution!");
}
ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: ARMBaseTargetMachine(T, TT, CPU, FS),
ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: ARMBaseTargetMachine(T, TT, CPU, FS, RM),
InstrInfo(Subtarget.hasThumb2()
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
@ -179,10 +176,6 @@ bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) {
// FIXME: Move this to TargetJITInfo!
if (DefRelocModel == Reloc::Default)
setRelocationModel(Reloc::Static);
// Machine code emitter pass for ARM.
PM.add(createARMJITCodeEmitterPass(*this, JCE));
return false;

13
lib/Target/ARM/ARMTargetMachine.h
View File

@ -37,11 +37,10 @@ protected:
private:
ARMJITInfo JITInfo;
InstrItineraryData InstrItins;
Reloc::Model DefRelocModel; // Reloc model before it's overridden.
public:
ARMBaseTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
@ -69,8 +68,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
ARMSelectionDAGInfo TSInfo;
ARMFrameLowering FrameLowering;
public:
ARMTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
ARMTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const ARMRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
@ -108,8 +107,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine {
// Either Thumb1FrameLowering or ARMFrameLowering.
OwningPtr<ARMFrameLowering> FrameLowering;
public:
ThumbTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
virtual const ARMBaseRegisterInfo *getRegisterInfo() const {

2
lib/Target/ARM/AsmParser/ARMAsmLexer.cpp
View File

@ -15,7 +15,7 @@
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/Target/TargetAsmLexer.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetMachine.h" // FIXME
#include "llvm/Target/TargetRegistry.h"
#include "llvm/ADT/OwningPtr.h"

14
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -142,3 +142,17 @@ extern "C" void LLVMInitializeARMMCAsmInfo() {
RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
}
MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::DynamicNoPIC;
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeARMMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
}

10
lib/Target/Alpha/AlphaTargetMachine.cpp
View File

@ -22,19 +22,17 @@ extern "C" void LLVMInitializeAlphaTarget() {
RegisterTargetMachine<AlphaTargetMachine> X(TheAlphaTarget);
}
AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: LLVMTargetMachine(T, TT, CPU, FS),
AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
DataLayout("e-f128:128:128-n64"),
FrameLowering(Subtarget),
Subtarget(TT, CPU, FS),
TLInfo(*this),
TSInfo(*this) {
setRelocationModel(Reloc::PIC_);
}
//===----------------------------------------------------------------------===//
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//

4
lib/Target/Alpha/AlphaTargetMachine.h
View File

@ -36,8 +36,8 @@ class AlphaTargetMachine : public LLVMTargetMachine {
AlphaSelectionDAGInfo TSInfo;
public:
AlphaTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
AlphaTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {

12
lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp
View File

@ -65,3 +65,15 @@ extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
extern "C" void LLVMInitializeAlphaMCAsmInfo() {
RegisterMCAsmInfo<AlphaMCAsmInfo> X(TheAlphaTarget);
}
MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(Reloc::PIC_);
return X;
}
extern "C" void LLVMInitializeAlphaMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheAlphaTarget,
createAlphaMCCodeGenInfo);
}

8
lib/Target/Blackfin/BlackfinTargetMachine.cpp
View File

@ -22,10 +22,10 @@ extern "C" void LLVMInitializeBlackfinTarget() {
}
BlackfinTargetMachine::BlackfinTargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: LLVMTargetMachine(T, TT, CPU, FS),
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
DataLayout("e-p:32:32-i64:32-f64:32-n32"),
Subtarget(TT, CPU, FS),
TLInfo(*this),

4
lib/Target/Blackfin/BlackfinTargetMachine.h
View File

@ -35,8 +35,8 @@ namespace llvm {
BlackfinFrameLowering FrameLowering;
BlackfinIntrinsicInfo IntrinsicInfo;
public:
BlackfinTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
BlackfinTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {

11
lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp
View File

@ -68,3 +68,14 @@ extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
extern "C" void LLVMInitializeBlackfinMCAsmInfo() {
RegisterMCAsmInfo<BlackfinMCAsmInfo> X(TheBlackfinTarget);
}
MCCodeGenInfo *createBlackfinMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeBlackfinMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheBlackfinTarget,
createBlackfinMCCodeGenInfo);
}

2
lib/Target/CBackend/CBackend.cpp
View File

@ -71,6 +71,8 @@ extern "C" void LLVMInitializeCBackendMCInstrInfo() {}
extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {}
extern "C" void LLVMInitializeCBackendMCCodeGenInfo() {}
namespace {
class CBEMCAsmInfo : public MCAsmInfo {
public:

4
lib/Target/CBackend/CTargetMachine.h
View File

@ -20,8 +20,8 @@
namespace llvm {
struct CTargetMachine : public TargetMachine {
CTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS)
CTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM)
: TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,

13
lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp
View File

@ -77,3 +77,16 @@ static MCAsmInfo *createSPUMCAsmInfo(const Target &T, StringRef TT) {
extern "C" void LLVMInitializeCellSPUMCAsmInfo() {
RegisterMCAsmInfoFn X(TheCellSPUTarget, createSPUMCAsmInfo);
}
MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
// For the time being, use static relocations, since there's really no
// support for PIC yet.
X->InitMCCodeGenInfo(Reloc::Static);
return X;
}
extern "C" void LLVMInitializeCellSPUMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheCellSPUTarget,
createSPUMCCodeGenInfo);
}

9
lib/Target/CellSPU/SPUTargetMachine.cpp
View File

@ -31,9 +31,9 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const {
return &LR[0];
}
SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,const std::string &FS)
: LLVMTargetMachine(T, TT, CPU, FS),
SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU,StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS),
DataLayout(Subtarget.getTargetDataString()),
InstrInfo(*this),
@ -41,9 +41,6 @@ SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT,
TLInfo(*this),
TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
// For the time being, use static relocations, since there's really no
// support for PIC yet.
setRelocationModel(Reloc::Static);
}
//===----------------------------------------------------------------------===//

4
lib/Target/CellSPU/SPUTargetMachine.h
View File

@ -38,8 +38,8 @@ class SPUTargetMachine : public LLVMTargetMachine {
SPUSelectionDAGInfo TSInfo;
InstrItineraryData InstrItins;
public:
SPUTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
SPUTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
/// Return the subtarget implementation object
virtual const SPUSubtarget *getSubtargetImpl() const {

2
lib/Target/CppBackend/CPPBackend.cpp
View File

@ -85,6 +85,8 @@ extern "C" void LLVMInitializeCppBackendMCInstrInfo() {}
extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {}
extern "C" void LLVMInitializeCppBackendMCCodeGenInfo() {}
namespace {
typedef std::vector<Type*> TypeList;
typedef std::map<Type*,std::string> TypeMap;

4
lib/Target/CppBackend/CPPTargetMachine.h
View File

@ -22,8 +22,8 @@ namespace llvm {
class formatted_raw_ostream;
struct CPPTargetMachine : public TargetMachine {
CPPTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS)
CPPTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM)
: TargetMachine(T, TT, CPU, FS) {}
virtual bool addPassesToEmitFile(PassManagerBase &PM,

2
lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp
View File

@ -19,7 +19,7 @@
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/Target/TargetAsmLexer.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetMachine.h" // FIXME
#include "llvm/Target/TargetRegistry.h"
#include <string>

10
lib/Target/MBlaze/MBlazeTargetMachine.cpp
View File

@ -67,19 +67,15 @@ extern "C" void LLVMInitializeMBlazeTarget() {
// offset from the stack/frame pointer, using StackGrowsUp enables
// an easier handling.
MBlazeTargetMachine::
MBlazeTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS):
LLVMTargetMachine(T, TT, CPU, FS),
MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM):
LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS),
DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"),
InstrInfo(*this),
FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
if (getRelocationModel() == Reloc::Default) {
setRelocationModel(Reloc::Static);
}
if (getCodeModel() == CodeModel::Default)
setCodeModel(CodeModel::Small);
}

4
lib/Target/MBlaze/MBlazeTargetMachine.h
View File

@ -41,8 +41,8 @@ namespace llvm {
InstrItineraryData InstrItins;
public:
MBlazeTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
MBlazeTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const MBlazeInstrInfo *getInstrInfo() const
{ return &InstrInfo; }

13
lib/Target/MBlaze/MCTargetDesc/MBlazeMCTargetDesc.cpp
View File

@ -74,3 +74,16 @@ static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
extern "C" void LLVMInitializeMBlazeMCAsmInfo() {
RegisterMCAsmInfoFn X(TheMBlazeTarget, createMCAsmInfo);
}
MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::Static;
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeMBlazeMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheMBlazeTarget,
createMBlazeMCCodeGenInfo);
}

11
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
View File

@ -66,3 +66,14 @@ extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
extern "C" void LLVMInitializeMSP430MCAsmInfo() {
RegisterMCAsmInfo<MSP430MCAsmInfo> X(TheMSP430Target);
}
MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeMSP430MCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheMSP430Target,
createMSP430MCCodeGenInfo);
}

8
lib/Target/MSP430/MSP430TargetMachine.cpp
View File

@ -25,10 +25,10 @@ extern "C" void LLVMInitializeMSP430Target() {
}
MSP430TargetMachine::MSP430TargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: LLVMTargetMachine(T, TT, CPU, FS),
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS),
// FIXME: Check TargetData string.
DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"),

4
lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -38,8 +38,8 @@ class MSP430TargetMachine : public LLVMTargetMachine {
MSP430FrameLowering FrameLowering;
public:
MSP430TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
MSP430TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;

21
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -77,3 +77,24 @@ extern "C" void LLVMInitializeMipsMCAsmInfo() {
RegisterMCAsmInfoFn X(TheMipsTarget, createMipsMCAsmInfo);
RegisterMCAsmInfoFn Y(TheMipselTarget, createMipsMCAsmInfo);
}
MCCodeGenInfo *createMipsMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) {
// Abicall enables PIC by default
if (TT.find("mipsallegrex") != std::string::npos ||
TT.find("psp") != std::string::npos)
RM = Reloc::Static;
else
RM = Reloc::PIC_;
}
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeMipsMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheMipsTarget,
createMipsMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheMipselTarget,
createMipsMCCodeGenInfo);
}

19
lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -31,10 +31,10 @@ extern "C" void LLVMInitializeMipsTarget() {
// an easier handling.
// Using CodeModel::Large enables different CALL behavior.
MipsTargetMachine::
MipsTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS,
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM,
bool isLittle=false):
LLVMTargetMachine(T, TT, CPU, FS),
LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS, isLittle),
DataLayout(isLittle ?
std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
@ -42,19 +42,12 @@ MipsTargetMachine(const Target &T, const std::string &TT,
InstrInfo(*this),
FrameLowering(Subtarget),
TLInfo(*this), TSInfo(*this) {
// Abicall enables PIC by default
if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isABI_O32())
setRelocationModel(Reloc::PIC_);
else
setRelocationModel(Reloc::Static);
}
}
MipselTargetMachine::
MipselTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS) :
MipsTargetMachine(T, TT, CPU, FS, true) {}
MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM) :
MipsTargetMachine(T, TT, CPU, FS, RM, true) {}
// Install an instruction selector pass using
// the ISelDag to gen Mips code.

10
lib/Target/Mips/MipsTargetMachine.h
View File

@ -34,9 +34,9 @@ namespace llvm {
MipsTargetLowering TLInfo;
MipsSelectionDAGInfo TSInfo;
public:
MipsTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS,
bool isLittle);
MipsTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool isLittle);
virtual const MipsInstrInfo *getInstrInfo() const
{ return &InstrInfo; }
@ -73,8 +73,8 @@ namespace llvm {
///
class MipselTargetMachine : public MipsTargetMachine {
public:
MipselTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
MipselTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
};
} // End llvm namespace

11
lib/Target/PTX/MCTargetDesc/PTXMCTargetDesc.cpp
View File

@ -70,3 +70,14 @@ extern "C" void LLVMInitializePTXMCAsmInfo() {
RegisterMCAsmInfo<PTXMCAsmInfo> X(ThePTX32Target);
RegisterMCAsmInfo<PTXMCAsmInfo> Y(ThePTX64Target);
}
MCCodeGenInfo *createPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializePTXMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(ThePTX32Target, createPTXMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(ThePTX64Target, createPTXMCCodeGenInfo);
}

28
lib/Target/PTX/PTXTargetMachine.cpp
View File

@ -47,11 +47,11 @@ namespace {
// DataLayout and FrameLowering are filled with dummy data
PTXTargetMachine::PTXTargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS,
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS),
StringRef TT,
StringRef CPU,
StringRef FS,
Reloc::Model RM, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
DataLayout(is64Bit ? DataLayout64 : DataLayout32),
Subtarget(TT, CPU, FS, is64Bit),
FrameLowering(Subtarget),
@ -59,18 +59,16 @@ PTXTargetMachine::PTXTargetMachine(const Target &T,
TLInfo(*this) {
}
PTX32TargetMachine::PTX32TargetMachine(const Target &T,
const std::string& TT,
const std::string& CPU,
const std::string& FS)
: PTXTargetMachine(T, TT, CPU, FS, false) {
PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: PTXTargetMachine(T, TT, CPU, FS, RM, false) {
}
PTX64TargetMachine::PTX64TargetMachine(const Target &T,
const std::string& TT,
const std::string& CPU,
const std::string& FS)
: PTXTargetMachine(T, TT, CPU, FS, true) {
PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: PTXTargetMachine(T, TT, CPU, FS, RM, true) {
}
bool PTXTargetMachine::addInstSelector(PassManagerBase &PM,

12
lib/Target/PTX/PTXTargetMachine.h
View File

@ -32,8 +32,8 @@ class PTXTargetMachine : public LLVMTargetMachine {
PTXTargetLowering TLInfo;
public:
PTXTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS,
PTXTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM,
bool is64Bit);
virtual const TargetData *getTargetData() const { return &DataLayout; }
@ -61,15 +61,15 @@ class PTXTargetMachine : public LLVMTargetMachine {
class PTX32TargetMachine : public PTXTargetMachine {
public:
PTX32TargetMachine(const Target &T, const std::string &TT,
const std::string& CPU, const std::string& FS);
PTX32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
}; // class PTX32TargetMachine
class PTX64TargetMachine : public PTXTargetMachine {
public:
PTX64TargetMachine(const Target &T, const std::string &TT,
const std::string& CPU, const std::string& FS);
PTX64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
}; // class PTX32TargetMachine
} // namespace llvm

19
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -93,3 +93,22 @@ extern "C" void LLVMInitializePowerPCMCAsmInfo() {
RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo);
RegisterMCAsmInfoFn D(ThePPC64Target, createPPCMCAsmInfo);
}
MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default) {
Triple T(TT);
if (T.isOSDarwin())
RM = Reloc::DynamicNoPIC;
else
RM = Reloc::Static;
}
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializePowerPCMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(ThePPC32Target, createPPCMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(ThePPC64Target, createPPCMCCodeGenInfo);
}

42
lib/Target/PowerPC/PPCTargetMachine.cpp
View File

@ -52,40 +52,32 @@ extern "C" void LLVMInitializePowerPCTarget() {
TargetRegistry::RegisterObjectStreamer(ThePPC64Target, createMCStreamer);
}
PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS),
PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS, is64Bit),
DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
TLInfo(*this), TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isDarwin())
setRelocationModel(Reloc::DynamicNoPIC);
else
setRelocationModel(Reloc::Static);
}
}
/// Override this for PowerPC. Tail merging happily breaks up instruction issue
/// groups, which typically degrades performance.
bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: PPCTargetMachine(T, TT, CPU, FS, false) {
PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: PPCTargetMachine(T, TT, CPU, FS, RM, false) {
}
PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: PPCTargetMachine(T, TT, CPU, FS, true) {
PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: PPCTargetMachine(T, TT, CPU, FS, RM, true) {
}
@ -110,19 +102,11 @@ bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) {
// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
// FIXME: This should be moved to TargetJITInfo!!
if (Subtarget.isPPC64()) {
// We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
// instructions to materialize arbitrary global variable + function +
// constant pool addresses.
setRelocationModel(Reloc::PIC_);
if (Subtarget.isPPC64())
// Temporary workaround for the inability of PPC64 JIT to handle jump
// tables.
DisableJumpTables = true;
} else {
setRelocationModel(Reloc::Static);
}
// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
// writing?

14
lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -40,9 +40,9 @@ class PPCTargetMachine : public LLVMTargetMachine {
InstrItineraryData InstrItins;
public:
PPCTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS,
bool is64Bit);
PPCTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit);
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const PPCFrameLowering *getFrameLowering() const {
@ -77,16 +77,16 @@ public:
///
class PPC32TargetMachine : public PPCTargetMachine {
public:
PPC32TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
PPC32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
};
/// PPC64TargetMachine - PowerPC 64-bit target machine.
///
class PPC64TargetMachine : public PPCTargetMachine {
public:
PPC64TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
PPC64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
};
} // end namespace llvm

14
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -65,3 +65,17 @@ extern "C" void LLVMInitializeSparcMCAsmInfo() {
RegisterMCAsmInfo<SparcELFMCAsmInfo> X(TheSparcTarget);
RegisterMCAsmInfo<SparcELFMCAsmInfo> Y(TheSparcV9Target);
}
MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeSparcMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget,
createSparcMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target,
createSparcMCCodeGenInfo);
}

24
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -24,10 +24,10 @@ extern "C" void LLVMInitializeSparcTarget() {
/// SparcTargetMachine ctor - Create an ILP32 architecture model
///
SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS, bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS),
SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS, is64bit),
DataLayout(Subtarget.getDataLayout()),
TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
@ -51,15 +51,15 @@ bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
}
SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: SparcTargetMachine(T, TT, CPU, FS, false) {
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: SparcTargetMachine(T, TT, CPU, FS, RM, false) {
}
SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: SparcTargetMachine(T, TT, CPU, FS, true) {
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: SparcTargetMachine(T, TT, CPU, FS, RM, true) {
}

14
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -33,9 +33,9 @@ class SparcTargetMachine : public LLVMTargetMachine {
SparcInstrInfo InstrInfo;
SparcFrameLowering FrameLowering;
public:
SparcTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS,
bool is64bit);
SparcTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64bit);
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
@ -62,16 +62,16 @@ public:
///
class SparcV8TargetMachine : public SparcTargetMachine {
public:
SparcV8TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
SparcV8TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
};
/// SparcV9TargetMachine - Sparc 64-bit target machine
///
class SparcV9TargetMachine : public SparcTargetMachine {
public:
SparcV9TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
SparcV9TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
};
} // end namespace llvm

13
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View File

@ -67,3 +67,16 @@ extern "C" void LLVMInitializeSystemZMCSubtargetInfo() {
extern "C" void LLVMInitializeSystemZMCAsmInfo() {
RegisterMCAsmInfo<SystemZMCAsmInfo> X(TheSystemZTarget);
}
MCCodeGenInfo *createSystemZMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
if (RM == Reloc::Default)
RM = Reloc::Static;
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeSystemZMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheSystemZTarget,
createSystemZMCCodeGenInfo);
}

11
lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -21,18 +21,15 @@ extern "C" void LLVMInitializeSystemZTarget() {
/// SystemZTargetMachine ctor - Create an ILP64 architecture model
///
SystemZTargetMachine::SystemZTargetMachine(const Target &T,
const std::string &TT,
const std::string &CPU,
const std::string &FS)
: LLVMTargetMachine(T, TT, CPU, FS),
StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS),
DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
"-f64:64:64-f128:128:128-a0:16:16-n32:64"),
InstrInfo(*this), TLInfo(*this), TSInfo(*this),
FrameLowering(Subtarget) {
if (getRelocationModel() == Reloc::Default)
setRelocationModel(Reloc::Static);
}
bool SystemZTargetMachine::addInstSelector(PassManagerBase &PM,

4
lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -37,8 +37,8 @@ class SystemZTargetMachine : public LLVMTargetMachine {
SystemZSelectionDAGInfo TSInfo;
SystemZFrameLowering FrameLowering;
public:
SystemZTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
SystemZTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const TargetFrameLowering *getFrameLowering() const {
return &FrameLowering;

27
lib/Target/TargetMachine.cpp
View File

@ -40,7 +40,6 @@ namespace llvm {
bool JITExceptionHandling;
bool JITEmitDebugInfo;
bool JITEmitDebugInfoToDisk;
Reloc::Model RelocationModel;
CodeModel::Model CMModel;
bool GuaranteedTailCallOpt;
unsigned StackAlignmentOverride;
@ -143,21 +142,6 @@ EmitJitDebugInfoToDisk("jit-emit-debug-to-disk",
cl::location(JITEmitDebugInfoToDisk),
cl::init(false));
static cl::opt<llvm::Reloc::Model, true>
DefRelocationModel("relocation-model",
cl::desc("Choose relocation model"),
cl::location(RelocationModel),
cl::init(Reloc::Default),
cl::values(
clEnumValN(Reloc::Default, "default",
"Target default relocation model"),
clEnumValN(Reloc::Static, "static",
"Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
static cl::opt<llvm::CodeModel::Model, true>
DefCodeModel("code-model",
cl::desc("Choose code model"),
@ -236,13 +220,10 @@ TargetMachine::~TargetMachine() {
/// getRelocationModel - Returns the code generation relocation model. The
/// choices are static, PIC, and dynamic-no-pic, and target default.
Reloc::Model TargetMachine::getRelocationModel() {
return RelocationModel;
}
/// setRelocationModel - Sets the code generation relocation model.
void TargetMachine::setRelocationModel(Reloc::Model Model) {
RelocationModel = Model;
Reloc::Model TargetMachine::getRelocationModel() const {
if (!CodeGenInfo)
return Reloc::Default;
return CodeGenInfo->getRelocationModel();
}
/// getCodeModel - Returns the code model. The choices are small, kernel,

47
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -338,3 +338,50 @@ extern "C" void LLVMInitializeX86MCAsmInfo() {
RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
}
MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
Triple T(TT);
bool is64Bit = T.getArch() == Triple::x86_64;
if (RM == Reloc::Default) {
// Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
// Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
// use static relocation model by default.
if (T.isOSDarwin()) {
if (is64Bit)
RM = Reloc::PIC_;
else
RM = Reloc::DynamicNoPIC;
} else if (T.isOSWindows() && is64Bit)
RM = Reloc::PIC_;
else
RM = Reloc::Static;
}
// ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
// is defined as a model for code which may be used in static or dynamic
// executables but not necessarily a shared library. On X86-32 we just
// compile in -static mode, in x86-64 we use PIC.
if (RM == Reloc::DynamicNoPIC) {
if (is64Bit)
RM = Reloc::PIC_;
else if (!T.isOSDarwin())
RM = Reloc::Static;
}
// If we are on Darwin, disallow static relocation model in X86-64 mode, since
// the Mach-O file format doesn't support it.
if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
RM = Reloc::PIC_;
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeX86MCCodeGenInfo() {
// Register the target asm info.
RegisterMCCodeGenInfoFn A(TheX86_32Target, createX86MCCodeGenInfo);
RegisterMCCodeGenInfoFn B(TheX86_64Target, createX86MCCodeGenInfo);
}

76
lib/Target/X86/X86TargetMachine.cpp
View File

@ -65,10 +65,10 @@ extern "C" void LLVMInitializeX86Target() {
}
X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: X86TargetMachine(T, TT, CPU, FS, false),
X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: X86TargetMachine(T, TT, CPU, FS, RM, false),
DataLayout(getSubtargetImpl()->isTargetDarwin() ?
"e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" :
(getSubtargetImpl()->isTargetCygMing() ||
@ -82,10 +82,10 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT,
}
X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: X86TargetMachine(T, TT, CPU, FS, true),
X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM)
: X86TargetMachine(T, TT, CPU, FS, RM, true),
DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"),
InstrInfo(*this),
TSInfo(*this),
@ -95,52 +95,13 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT,
/// X86TargetMachine ctor - Create an X86 target.
///
X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS),
X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
FrameLowering(*this, Subtarget),
ELFWriterInfo(is64Bit, true) {
DefRelocModel = getRelocationModel();
// If no relocation model was picked, default as appropriate for the target.
if (getRelocationModel() == Reloc::Default) {
// Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
// Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
// use static relocation model by default.
if (Subtarget.isTargetDarwin()) {
if (Subtarget.is64Bit())
setRelocationModel(Reloc::PIC_);
else
setRelocationModel(Reloc::DynamicNoPIC);
} else if (Subtarget.isTargetWin64())
setRelocationModel(Reloc::PIC_);
else
setRelocationModel(Reloc::Static);
}
assert(getRelocationModel() != Reloc::Default &&
"Relocation mode not picked");
// ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
// is defined as a model for code which may be used in static or dynamic
// executables but not necessarily a shared library. On X86-32 we just
// compile in -static mode, in x86-64 we use PIC.
if (getRelocationModel() == Reloc::DynamicNoPIC) {
if (is64Bit)
setRelocationModel(Reloc::PIC_);
else if (!Subtarget.isTargetDarwin())
setRelocationModel(Reloc::Static);
}
// If we are on Darwin, disallow static relocation model in X86-64 mode, since
// the Mach-O file format doesn't support it.
if (getRelocationModel() == Reloc::Static &&
Subtarget.isTargetDarwin() &&
is64Bit)
setRelocationModel(Reloc::PIC_);
// Determine the PICStyle based on the target selected.
if (getRelocationModel() == Reloc::Static) {
// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
@ -161,10 +122,6 @@ X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
Subtarget.setPICStyle(PICStyles::GOT);
}
// Finally, if we have "none" as our PIC style, force to static mode.
if (Subtarget.getPICStyle() == PICStyles::None)
setRelocationModel(Reloc::Static);
// default to hard float ABI
if (FloatABIType == FloatABI::Default)
FloatABIType = FloatABI::Hard;
@ -210,15 +167,6 @@ bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,
JITCodeEmitter &JCE) {
// FIXME: Move this to TargetJITInfo!
// On Darwin, do not override 64-bit setting made in X86TargetMachine().
if (DefRelocModel == Reloc::Default &&
(!Subtarget.isTargetDarwin() || !Subtarget.is64Bit())) {
setRelocationModel(Reloc::Static);
Subtarget.setPICStyle(PICStyles::None);
}
PM.add(createX86JITCodeEmitterPass(*this, JCE));
return false;

16
lib/Target/X86/X86TargetMachine.h
View File

@ -29,12 +29,12 @@
namespace llvm {
class formatted_raw_ostream;
class StringRef;
class X86TargetMachine : public LLVMTargetMachine {
X86Subtarget Subtarget;
X86FrameLowering FrameLowering;
X86ELFWriterInfo ELFWriterInfo;
Reloc::Model DefRelocModel; // Reloc model before it's overridden.
private:
// We have specific defaults for X86.
@ -42,9 +42,9 @@ private:
virtual void setCodeModelForStatic();
public:
X86TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS,
bool is64Bit);
X86TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS,
Reloc::Model RM, bool is64Bit);
virtual const X86InstrInfo *getInstrInfo() const {
llvm_unreachable("getInstrInfo not implemented");
@ -87,8 +87,8 @@ class X86_32TargetMachine : public X86TargetMachine {
X86TargetLowering TLInfo;
X86JITInfo JITInfo;
public:
X86_32TargetMachine(const Target &T, const std::string &M,
const std::string &CPU, const std::string &FS);
X86_32TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
@ -113,8 +113,8 @@ class X86_64TargetMachine : public X86TargetMachine {
X86TargetLowering TLInfo;
X86JITInfo JITInfo;
public:
X86_64TargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
X86_64TargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;

11
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View File

@ -75,3 +75,14 @@ static MCAsmInfo *createXCoreMCAsmInfo(const Target &T, StringRef TT) {
extern "C" void LLVMInitializeXCoreMCAsmInfo() {
RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo);
}
MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM) {
MCCodeGenInfo *X = new MCCodeGenInfo();
X->InitMCCodeGenInfo(RM);
return X;
}
extern "C" void LLVMInitializeXCoreMCCodeGenInfo() {
TargetRegistry::RegisterMCCodeGenInfo(TheXCoreTarget,
createXCoreMCCodeGenInfo);
}

8
lib/Target/XCore/XCoreTargetMachine.cpp
View File

@ -19,10 +19,10 @@ using namespace llvm;
/// XCoreTargetMachine ctor - Create an ILP32 architecture model
///
XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU,
const std::string &FS)
: LLVMTargetMachine(T, TT, CPU, FS),
XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU,
StringRef FS, Reloc::Model RM)
: LLVMTargetMachine(T, TT, CPU, FS, RM),
Subtarget(TT, CPU, FS),
DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"),

4
lib/Target/XCore/XCoreTargetMachine.h
View File

@ -32,8 +32,8 @@ class XCoreTargetMachine : public LLVMTargetMachine {
XCoreTargetLowering TLInfo;
XCoreSelectionDAGInfo TSInfo;
public:
XCoreTargetMachine(const Target &T, const std::string &TT,
const std::string &CPU, const std::string &FS);
XCoreTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, Reloc::Model RM);
virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const XCoreFrameLowering *getFrameLowering() const {

1
test/CodeGen/Thumb2/thumb2-bcc.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it
; If-conversion defeats the purpose of this test, which is to check CBZ
; generation, so use memory barrier instruction to make sure it doesn't
; happen and we get actual branches.

18
tools/llc/llc.cpp
View File

@ -76,6 +76,21 @@ MAttrs("mattr",
cl::desc("Target specific attributes (-mattr=help for details)"),
cl::value_desc("a1,+a2,-a3,..."));
static cl::opt<Reloc::Model>
RelocModel("relocation-model",
cl::desc("Choose relocation model"),
cl::init(Reloc::Default),
cl::values(
clEnumValN(Reloc::Default, "default",
"Target default relocation model"),
clEnumValN(Reloc::Static, "static",
"Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
static cl::opt<bool>
RelaxAll("mc-relax-all",
cl::desc("When used with filetype=obj, "
@ -202,6 +217,7 @@ int main(int argc, char **argv) {
// Initialize targets first, so that --version shows registered targets.
InitializeAllTargets();
InitializeAllMCAsmInfos();
InitializeAllMCCodeGenInfos();
InitializeAllMCSubtargetInfos();
InitializeAllAsmPrinters();
InitializeAllAsmParsers();
@ -272,7 +288,7 @@ int main(int argc, char **argv) {
std::auto_ptr<TargetMachine>
target(TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU,
FeaturesStr));
FeaturesStr, RelocModel));
assert(target.get() && "Could not allocate target machine!");
TargetMachine &Target = *target.get();

16
tools/lli/lli.cpp
View File

@ -108,6 +108,21 @@ namespace {
NoLazyCompilation("disable-lazy-compilation",
cl::desc("Disable JIT lazy compilation"),
cl::init(false));
cl::opt<Reloc::Model>
RelocModel("relocation-model",
cl::desc("Choose relocation model"),
cl::init(Reloc::Default),
cl::values(
clEnumValN(Reloc::Default, "default",
"Target default relocation model"),
clEnumValN(Reloc::Static, "static",
"Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
}
static ExecutionEngine *EE = 0;
@ -164,6 +179,7 @@ int main(int argc, char **argv, char * const *envp) {
builder.setMArch(MArch);
builder.setMCPU(MCPU);
builder.setMAttrs(MAttrs);
builder.setRelocationModel(RelocModel);
builder.setErrorStr(&ErrorMsg);
builder.setEngineKind(ForceInterpreter
? EngineKind::Interpreter

19
tools/llvm-mc/llvm-mc.cpp
View File

@ -111,6 +111,21 @@ MCPU("mcpu",
cl::value_desc("cpu-name"),
cl::init(""));
static cl::opt<Reloc::Model>
RelocModel("relocation-model",
cl::desc("Choose relocation model"),
cl::init(Reloc::Default),
cl::values(
clEnumValN(Reloc::Default, "default",
"Target default relocation model"),
clEnumValN(Reloc::Static, "static",
"Non-relocatable code"),
clEnumValN(Reloc::PIC_, "pic",
"Fully relocatable, position independent code"),
clEnumValN(Reloc::DynamicNoPIC, "dynamic-no-pic",
"Relocatable external references, non-relocatable code"),
clEnumValEnd));
static cl::opt<bool>
NoInitialTextSection("n", cl::desc("Don't assume assembly file starts "
"in the text section"));
@ -321,7 +336,8 @@ static int AssembleInput(const char *ProgName) {
// the .cpu and .code16 directives).
OwningPtr<TargetMachine> TM(TheTarget->createTargetMachine(TripleName,
MCPU,
FeaturesStr));
FeaturesStr,
RelocModel));
if (!TM) {
errs() << ProgName << ": error: could not create target for triple '"
@ -440,6 +456,7 @@ int main(int argc, char **argv) {
// FIXME: We shouldn't need to initialize the Target(Machine)s.
llvm::InitializeAllTargets();
llvm::InitializeAllMCAsmInfos();
llvm::InitializeAllMCCodeGenInfos();
llvm::InitializeAllMCInstrInfos();
llvm::InitializeAllMCRegisterInfos();
llvm::InitializeAllMCSubtargetInfos();

1
tools/llvm-objdump/llvm-objdump.cpp
View File

@ -270,6 +270,7 @@ int main(int argc, char **argv) {
// FIXME: We shouldn't need to initialize the Target(Machine)s.
llvm::InitializeAllTargets();
llvm::InitializeAllMCAsmInfos();
llvm::InitializeAllMCCodeGenInfos();
llvm::InitializeAllAsmPrinters();
llvm::InitializeAllAsmParsers();
llvm::InitializeAllDisassemblers();

11
tools/lto/LTOCodeGenerator.cpp
View File

@ -75,6 +75,7 @@ LTOCodeGenerator::LTOCodeGenerator()
{
InitializeAllTargets();
InitializeAllMCAsmInfos();
InitializeAllMCCodeGenInfos();
InitializeAllMCRegisterInfos();
InitializeAllMCSubtargetInfos();
InitializeAllAsmPrinters();
@ -252,15 +253,16 @@ bool LTOCodeGenerator::determineTarget(std::string& errMsg)
// The relocation model is actually a static member of TargetMachine
// and needs to be set before the TargetMachine is instantiated.
Reloc::Model RelocModel = Reloc::Default;
switch( _codeModel ) {
case LTO_CODEGEN_PIC_MODEL_STATIC:
TargetMachine::setRelocationModel(Reloc::Static);
RelocModel = Reloc::Static;
break;
case LTO_CODEGEN_PIC_MODEL_DYNAMIC:
TargetMachine::setRelocationModel(Reloc::PIC_);
RelocModel = Reloc::PIC_;
break;
case LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC:
TargetMachine::setRelocationModel(Reloc::DynamicNoPIC);
RelocModel = Reloc::DynamicNoPIC;
break;
}
@ -268,7 +270,8 @@ bool LTOCodeGenerator::determineTarget(std::string& errMsg)
SubtargetFeatures Features;
Features.getDefaultSubtargetFeatures(llvm::Triple(Triple));
std::string FeatureStr = Features.getString();
_target = march->createTargetMachine(Triple, _mCpu, FeatureStr);
_target = march->createTargetMachine(Triple, _mCpu, FeatureStr,
RelocModel);
}
return false;
}

1
tools/lto/LTOModule.cpp
View File

@ -136,6 +136,7 @@ LTOModule *LTOModule::makeLTOModule(MemoryBuffer *buffer,
static bool Initialized = false;
if (!Initialized) {
InitializeAllTargets();
InitializeAllMCCodeGenInfos();
InitializeAllMCAsmInfos();
InitializeAllMCSubtargetInfos();
InitializeAllAsmParsers();