Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15626 91177308-0d34-0410-b5e6-96231b3b80d8
Use a PowerPC specific prolog epilog inserter to control where spilled
callee save regs are placed on the stack.
Get rid of implicit return address stack slot, save return address reg
(LR) in appropriate slot
Improve code generated for functions that don't have calls or access
globals
Note from Chris: PowerPCPEI will eventually be eliminated, once the
functionality is merged into CodeGen/PrologEpilogInserter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15536 91177308-0d34-0410-b5e6-96231b3b80d8
* sumarray2d fixed: large fixed-size alloca
* make is now compileable
* Re-organized tests to fit them under proper headings
Patch by Nate Begeman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15347 91177308-0d34-0410-b5e6-96231b3b80d8
