Commit Graph

24 Commits

Author SHA1 Message Date
Andrew Trick
2da8bc8a5f Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 05:03:26 +00:00
Andrew Trick
6e8f4c4048 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24 04:28:06 +00:00
Evan Cheng
3881cb7a5d Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-29 22:42:35 +00:00
Bob Wilson
064312de86 Spelling fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 16:28:21 +00:00
Evan Cheng
3ef1c8759a Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10 01:29:16 +00:00
Evan Cheng
5f54ce3473 For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09 18:18:55 +00:00
Chris Lattner
5ca96988b0 declare a class with 'class' instead of struct to avoid tag mismatch
warnings, and don't shift by a bool.  Patch by Rizky Herucakra!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-12 15:46:56 +00:00
Anton Korobeynikov
96085a36db Initial support for different kinds of FU reservation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:19:32 +00:00
David Goodwin
1f52895692 Make the end-of-itinerary mark explicit. Some cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-24 20:22:50 +00:00
David Goodwin
dc4bdcdef1 Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 16:08:58 +00:00
David Goodwin
fac8541dd4 Extend the instruction itinerary model to include the ability to indicate the def and use cycle for each operand. This additional information is optional, so existing itineraries do not need to be changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79247 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-17 16:02:57 +00:00
David Goodwin
1a8f36e3ce Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-12 18:31:53 +00:00
David Goodwin
d94a4e5d8d Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78563 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 15:55:25 +00:00
Dan Gohman
c8c2827993 Implement ComputeLatency for MachineInstr ScheduleDAGs. Factor
some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59761 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21 00:12:10 +00:00
Dan Gohman
eb3904bc25 Delete redundant inline keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59754 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-20 22:10:21 +00:00
Dan Gohman
33372a18c5 Doxygenate comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59753 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-20 22:09:52 +00:00
Dan Gohman
cfbb2f074d A quick nm audit turned up several fixed tables and objects that were
marked read-write. Use const so that they can be allocated in a
read-only segment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48800 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-25 21:45:14 +00:00
Chris Lattner
7ed47a1335 Don't attribute in file headers anymore. See llvmdev for the
discussion of this change.  Boy are my fingers tired. ;-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 19:59:42 +00:00
Jeff Cohen
be07f72ca2 <cassert> no longer required to make VC++ happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24177 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-04 02:59:16 +00:00
Duraid Madina
0954038705 change NULL to 0, unbreaks the ppc target when building on ia64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24176 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-04 01:45:04 +00:00
Jim Laskey
7f39c14f52 1. Remove ranges from itinerary data.
2. Tidy up the subtarget emittined code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24172 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-03 22:47:41 +00:00
Jeff Cohen
55d1728ec8 Keep VC++ happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24148 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-02 04:03:16 +00:00
Jim Laskey
6cee630070 Allow itineraries to be passed through the Target Machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24139 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-01 20:06:59 +00:00
Jim Laskey
15517be4bf Structures used to hold scheduling information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24049 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-27 18:18:05 +00:00