Commit Graph

112879 Commits

Author SHA1 Message Date
Colin LeMahieu
a032778dcf [Hexagon] Adding vector shift instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227619 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 21:58:46 +00:00
Tom Stellard
24b999d7d0 R600/SI: Handle SI_SPILL_V96_RESTORE in SIRegisterInfo::eliminateFrameIndex()
This fixes a crash in Unigine Heaven.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227618 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 21:51:51 +00:00
Ahmed Bougacha
ee93f014cc [X86] Cleanup tabs in test vector-zext.ll. NFC.
Some tests have tabs, some don't.
In vector-[sz]ext.ll, space wins (well duh!).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227615 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 21:41:28 +00:00
Reid Kleckner
2389dc9d26 Silence "not all paths return a value" warning in MSVC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227614 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 21:30:57 +00:00
Colin LeMahieu
35e1281ec7 [Hexagon] Adding vector predicate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227613 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 21:24:06 +00:00
Colin LeMahieu
f99ddd0125 [Hexagon] Adding vector permutation instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227612 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 21:14:00 +00:00
Reid Kleckner
e359929517 Win64: Put a REX_W prefix on all TAILJMP* instructions
MSDN's x64 software conventions page says that this is one of the fixed
list of legal epilogues:
https://msdn.microsoft.com/en-us/library/tawsa7cb.aspx

Presumably this is how the unwinder distinguishes epilogue jumps from
in-function control flow.

Also normalize the way we place "## TAILCALL" comments on such jumps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227611 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 21:03:31 +00:00
Colin LeMahieu
a6c6e1ec6c [Hexagon] Adding vector multiplies. Cleaning up tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227609 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 20:56:54 +00:00
Yunzhong Gao
9dbaae6fae Remove the preverify pass from the documentation now that it has been removed
since r199487.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227608 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 20:51:09 +00:00
Colin LeMahieu
e288ebf31b [Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227607 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 20:08:37 +00:00
Chad Rosier
cea6171bda [AArch64] Make AArch64A57FPLoadBalancing output stable.
Add tie breaker to colorChainSet() sort so that processing order doesn't
depend on std::set order, which depends on pointer order, which is
unstable from run to run.

No test case as this is nearly impossible to reproduce.

Phabricator Review: http://reviews.llvm.org/D7265
Patch by Geoff Berry <gberry@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227606 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:55:40 +00:00
Adrian Prantl
aeeb71e276 Remove a redundant dyn_cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227605 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:42:59 +00:00
Adrian Prantl
88deac4007 Inliner: Use replaceDbgDeclareForAlloca() instead of splicing the
instruction and generalize it to optionally dereference the variable.
Follow-up to r227544.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227604 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:37:48 +00:00
Saleem Abdulrasool
7a3c3f3a96 ARM: further correct .fpu directive handling
If the original FPU specification involved a restricted VFP unit (d16), ensure
that we reset the functionality when we encounter a new FPU type.  In
particular, if the user specified vfpv3-d16, but switched to a VFPv3 (which has
32 double precision registers), we would fail to reset the D16 feature, and
treat it as being equivalent to vfpv3-d16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:35:18 +00:00
Renato Golin
88f1329e8c Revert "Add missing test from r227488"
This reverts commit r227489, since this is the real one failing the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227602 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:25:23 +00:00
Renato Golin
71b1347acb Revert "Revert "Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps.""
This reverts commit r227600, since that reverted the wrong comit. Sorry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227601 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:25:20 +00:00
Renato Golin
d0a4d9037b Revert "Matching ARM change for r227481: DebugInfo: Teach Fast ISel to respect the debug location of comparisons in jumps."
This reverts commit r227488 as it was failing ARM bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227600 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:18:58 +00:00
Alexey Samsonov
9b8adaf3b2 Fixup gold-plugin after r227576.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227599 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:14:04 +00:00
Colin LeMahieu
587083e6a4 [Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227598 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 19:13:26 +00:00
Saleem Abdulrasool
9492802a37 ARM: improve caret diagnostics for invalid FPU name
In the case of an invalid FPU name, place the caret at the name rather than FPU
directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227595 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 18:42:10 +00:00
Zachary Turner
728d12e435 Fix lli after the DebugInfo move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227594 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 18:42:03 +00:00
Filipe Cabecinhas
1897b5c08c Check bit widths before trying to get a type.
Added a test case for it.
Also added run lines for the test case in r227566.

Bugs found with afl-fuzz

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227589 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 18:13:50 +00:00
Colin LeMahieu
dd62b7ae96 [Hexagon] Adding a number of vector load variants and organizing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227588 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 18:09:44 +00:00
Zachary Turner
de20f59a2a Really really don't build llvm-pdbdump on MSVC < 2013.
I thought it was enough to just not add the tool subdirectory,
but apparently I need to explicitly mark it ignore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227587 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 18:08:05 +00:00
Zachary Turner
50418a0ac4 Move DebugInfo to DebugInfo/DWARF.
In preparation for adding PDB support to LLVM, this moves the
DWARF parsing code to its own subdirectory under DebugInfo, and
renames LLVMDebugInfo to LLVMDebugInfoDWARF.

This is purely a mechanical / build system change.

Differential Revision: http://reviews.llvm.org/D7269
Reviewed by: Eric Christopher

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227586 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 18:07:45 +00:00
Saleem Abdulrasool
8baa31e81c ARM: correct handling of .fpu directive
The FPU directive permits the user to switch the target FPU, enabling
instructions that would be otherwise unavailable.  However, when configuring the
new subtarget features, we would not enable the implied functions for newer
FPUs.  This would result in invalid rejection of valid input.  Ensure that we
inherit the implied FPU functionality when enabling newer versions of the FPU.
Fortunately, these are mostly hierarchical, unlike the CPUs.

Addresses PR22395.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227584 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 17:58:25 +00:00
Sanjay Patel
3460950d15 tidy up; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227582 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 16:58:58 +00:00
Chandler Carruth
b4a44570f6 [PM] Sink the population of the pass manager with target-specific
analyses back into the LTO code generator.

The pass manager builder (and the transforms library in general)
shouldn't be referencing the target machine at all.

This makes the LTO population work like the others -- the data layout
and target transform info need to be pre-populated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227576 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 13:33:42 +00:00
Chandler Carruth
2ec788d43f Fix a warning introduced by r227557 due to a default label in a fully
covering switch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227575 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 13:30:43 +00:00
NAKAMURA Takumi
d379c6b491 [Cygming] Seek also chkstk_ms, or JIT fails with DLL builds. It is fixup for r227519.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227574 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 13:01:19 +00:00
NAKAMURA Takumi
3703b1fa88 Regenerate configure since r227090.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227573 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 13:01:00 +00:00
Toma Tabacu
71dc8ece4f [mips] Manually replace JAL pseudo-instructions with their JALR equivalent, instead of using InstAlias.
Summary:
This is needed by the .cprestore assembler directive.

This directive needs to be able to insert an LW instruction after every JALR replacement of a JAL pseudo-instruction
(and never after a JALR which has NOT been a result of a pseudo-instruction replacement).

The problem with using InstAlias for these is that after it replaces the pseudo-instruction, we can't find out if the resulting JALR instruction
was generated by an InstAlias or not, so we don't know whether or not to insert our LW instruction.

By replacing it manually, we know when the pseudo-instruction replacement happens and we can insert the LW instruction correctly.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D5601

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227568 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 11:18:50 +00:00
Filipe Cabecinhas
8cf149dbad [bitcode reader] Fix an assert on invalid type tables
Bug found with afl-fuzz

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227566 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 10:57:58 +00:00
NAKAMURA Takumi
e21839b377 Introduce llvm/test/LTO/X86. LTO tests may be assumed as target-specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227564 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 10:09:26 +00:00
NAKAMURA Takumi
59288a4196 Introduce llvm/test/LTO/ARM for arm-specific LTO test(s).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227563 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 09:53:37 +00:00
Owen Anderson
bc227b65c2 Change a very hot piece of code in TableGen's register unit computations to use bit vectors rather than arrays.
For target descriptions with very large and very dense register files, TableGen
can take an extremely long time to run.  This change makes a dent in that (~15%
in my measurements) by accelerating the single hottest operation with better data
structures.

I believe there's still a lot of room to make this even faster with more global
changes that require replacing some of the existing datastructures in this area
with bit vectors, but that's a more involved change and I wanted to get this
simpler improvement in first.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227562 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 09:05:49 +00:00
Hao Liu
2f45a3c252 Move the target specific test case arbitrary-induction-step.ll to test/Transforms/LoopVectorize/AArch64 folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227561 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 07:33:31 +00:00
Hao Liu
e7769db118 [LoopVectorize] Induction variables: support arbitrary constant step.
Previously, only -1 and +1 step values are supported for induction variables. This patch extends LV to support
arbitrary constant steps.
Initial patch by Alexey Volkov. Some bug fixes are added in the following version.

Differential Revision: http://reviews.llvm.org/D6051 and http://reviews.llvm.org/D7193


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227557 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 05:02:21 +00:00
Hao Liu
7d3a44a692 [AArch64]Fix PR21675, a bug about lowering llvm.ctpop.i32. We should noot use "DAG.getUNDEF(MVT::v8i8)" to get all zero vector.
Patch by Wei-cheng Wang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227550 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 02:13:53 +00:00
Eric Christopher
dd5e9f624b Use the cached subtarget in PPCFrameLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227548 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 02:11:26 +00:00
Eric Christopher
87dd120c6a Migrate some of PPC away from the use of bare getSubtarget/getSubtargetImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227547 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 02:11:24 +00:00
Eric Christopher
31f58f2c74 Migrage PPCRegisterInfo to use the cached subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227546 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 02:11:21 +00:00
Adrian Prantl
e413c8afe0 Fix PR22386. The inliner moves static allocas to the entry basic block
so we need to move the dbg.declare intrinsics that describe them, too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:55:25 +00:00
Eric Christopher
99a3df3401 Migrate a bare getSubtarget call to query the MachineFunction
for the target dependent one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227542 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:50:09 +00:00
Eric Christopher
b42dc65111 Migrate NVPTXISelLowering to take the subtarget that it's dependent
upon as an argument and store/use that in the entire function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227541 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:50:07 +00:00
Eric Christopher
f66d626182 Remove unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227539 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:41:01 +00:00
Eric Christopher
7417d92e56 Migrate NVPTXISelDAGToDAG's getSubtarget to a runOnMachineFunction
version. Update NVPTXInstrInfo accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227538 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:40:59 +00:00
Eric Christopher
7c185f3674 Remove calls to bare getSubtarget and clean up the functions
accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227535 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:30:01 +00:00
Akira Hatanaka
6953381b0c [LTO] Scan all per-function subtargets when collecting runtime library names.
accumulateAndSortLibcalls in LTOCodeGenerator.cpp collects names of runtime
library functions which are used to identify user-defined functions that should
be protected. Previously, this function would only scan the TargetLowering
object belonging to the "main" subtarget for the library function names. This
commit changes it to scan all per-function subtargets.

Differential Revision: http://reviews.llvm.org/D7275


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227533 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:16:24 +00:00
Akira Hatanaka
31db3d6d62 [llvm-lto] Add a line for setting LTOCodeGenerator's CPU string from command
line.

This is needed for a test case I plan to commit later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227532 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-30 01:14:28 +00:00