Daniel Dunbar
77e2dd7bb2
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
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instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 20:44:16 +00:00
Daniel Dunbar
926f2bb3d8
X86-64: Mark WINCALL and more tail call instructions as code gen only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108685 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:07 +00:00
Daniel Dunbar
df4c47be29
X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:01 +00:00
Daniel Dunbar
cf246b7f0b
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 06:14:49 +00:00
Chris Lattner
599b531a96
Change LEA to have 5 operands for its memory operand, just
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like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 23:46:44 +00:00
Eric Christopher
fb31ccb68c
A slight reworking of the custom patterns for x86-64 tpoff codegen and
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correct the testcase for valid assembly.
Needs more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107860 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 07:36:46 +00:00
Bruno Cardoso Lopes
332fce49e3
Use only one multiclass to pinsrq instructions
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107750 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:43:01 +00:00
Bruno Cardoso Lopes
5e9fa98523
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 01:33:38 +00:00
Eric Christopher
37106afe02
Add a couple more quick comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 02:07:57 +00:00
Eric Christopher
749bb7e2d9
Update according to feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:49:35 +00:00
Eric Christopher
18ebf74781
Update uses, defs, and comments for darwin tls patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 08:01:49 +00:00
Eric Christopher
18fb00b4b9
Add some codegen patterns for x86_64-linux-gnu tls codegen matching.
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Based on a patch by Patrick Marlier!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 18:21:27 +00:00
Eric Christopher
f6bc0b9d4b
Remove isTwoAddress from 64-bit files.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:51:21 +00:00
Eric Christopher
f627dc37bf
Some assorted isTwoAddress -> Constraints cleanup.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 02:41:19 +00:00
Eric Christopher
544153653b
Ensure that mov and not lea are used to stick the address into
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the register. While we're at it, make sure it's in the right one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:04:25 +00:00
Eric Christopher
30ef0e5658
Add first pass at darwin tls compiler support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 04:07:48 +00:00
Daniel Dunbar
dcbab9cf5a
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
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to be matched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:21:28 +00:00
Kevin Enderby
04ac770be9
The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required
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for the 64-bit version of the Bit Test instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:16:58 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
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Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
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addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
4e7f8390c0
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:36:29 +00:00
Daniel Dunbar
1fe591da3e
X86: Model i64i32imm properly, as a subclass of all immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:39 +00:00
Daniel Dunbar
0306e3ddbf
X86: Fix immediate type of FOO64i32 operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:35 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Dan Gohman
100804f494
Set neverHasSideEffects on 64-bit pushf and popf, for consistency with
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16-bit and 32-bit pushf and popf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 15:42:55 +00:00
Dan Gohman
7f357ec6d2
Add mayLoad and mayStore flags to instructions which missed them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:34:55 +00:00
Chris Lattner
e1611f26e3
fix rdar://7947167 - llvm-mc doesn't match movsq
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 21:48:14 +00:00
Sean Callanan
1a8b789a4b
Eliminated the classification of control registers into %ecr_
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and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Kevin Enderby
a0161cd6f8
Fix to r102952. The MOV64toSDrm record in X86Instr64bit.td needed the opcode
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changed to 0x7E from 0x6E as well as the previous change of RPDI to S3SI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:42:46 +00:00
Kevin Enderby
eb612347f4
Fixed the encoding of two of the X86 movq instuctions. The Move quadword from
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mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect
encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-03 21:03:31 +00:00
Dan Gohman
71edb241a1
Remove the -disable-16bit command-line option, which is now obsolete.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 18:30:26 +00:00
Evan Cheng
2bce5f4b56
Enable i16 to i32 promotion by default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 08:30:49 +00:00
Evan Cheng
8b1190a540
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 01:18:01 +00:00
Chris Lattner
d486d77444
fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptest
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nodes all have an EFLAGS result when made by isel lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99736 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 05:07:17 +00:00
Chris Lattner
baba4bb72f
eliminate the last of the parallel's!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99700 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 02:47:14 +00:00
Chris Lattner
7e504141e0
remove 64-bit or_is_add parallels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-24 00:16:52 +00:00
Chris Lattner
99521af212
remove the patterns that I commented out in r98930, Dan verified
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that they are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99000 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 21:43:36 +00:00
Daniel Dunbar
0180daee02
MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 18:07:48 +00:00
Chris Lattner
1d7dbd1716
comment out a bunch of parallel store patterns that apparently
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can't match or just have no testcases. Will remove after
confirmation from dan that they really are dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98930 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 04:14:21 +00:00
Daniel Dunbar
c28c7689fc
X86: Fix encoding for TEST64rr.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98919 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 01:15:03 +00:00
Chris Lattner
e3486a4c9a
Now that tblgen can handle matching implicit defs of instructions
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to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.
Now we can change things like this:
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(X86cmp RFP80:$lhs, RFP80:$rhs),
- (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+ [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;
and fix terrible crimes like this:
-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
(TEST8rr GR8:$src1, GR8:$src1)>;
This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19 00:01:11 +00:00
Chris Lattner
e10038e54e
callq is pcrelative
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-18 17:52:22 +00:00
Chris Lattner
4d82068167
fix the same bug on the x86-64 side of the fence.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98616 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16 06:39:08 +00:00
Evan Cheng
700c71d2e8
Fix jit encoding bugs.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 19:28:34 +00:00
Evan Cheng
f48ef03655
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 03:48:46 +00:00
Daniel Dunbar
bf2d4c034d
X86_64: Fix encoding for the rest of the 64i32 instructions too.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 22:57:53 +00:00
Daniel Dunbar
859c9dc867
X86: Fix ADD64i32 encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 22:49:39 +00:00
Daniel Dunbar
96e2cec9c7
MC/X86_64: Fix matching of leaq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98444 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 19:31:44 +00:00
Daniel Dunbar
989ac72981
MC/X86_64: Fix matching of callq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 19:31:38 +00:00
Chris Lattner
341b27406d
Correct immediate sizes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97957 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 18:55:15 +00:00