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Commit Graph

10369 Commits

Author SHA1 Message Date
Evan Cheng
e0e925efb3 The "excess register pressure" returned by HighRegPressure() is not accurate enough to factor into scheduling priority. Eliminate it and add early exits to speed up scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 21:49:07 +00:00
Dan Gohman
7da5d3fc65 Handle Values with no value in getCopyFromRegs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 18:15:41 +00:00
Dan Gohman
ce0fe5da0d A block dominates itself, by definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109402 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 17:38:15 +00:00
Duncan Sands
b3893b193b Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess parameter)
may be used uninitialized in the callers of HighRegPressure.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109393 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 07:54:17 +00:00
Lang Hames
6f4e4df100 Factored out a bit of common code to mark VNInfos for deletion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109388 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 01:49:41 +00:00
Evan Cheng
e28ed16d25 Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109383 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-25 18:59:43 +00:00
Bob Wilson
3f92f73970 Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts on
those.  Radar 8231572.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-25 05:34:27 +00:00
Anton Korobeynikov
8c64b9766e Add hook to insert late LLVM=>LLVM passes just before isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 20:48:54 +00:00
Bob Wilson
f28dd88611 Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors
instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K
won't cause a compile time performance regression.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 06:01:53 +00:00
Devang Patel
2f58485fc8 Use current working directory when Dirname is empty. This only happens when absolute source file path is used on compiler command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109302 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 00:53:22 +00:00
Evan Cheng
70017e44cd Add an ILP scheduler. This is a register pressure aware scheduler that's
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.

On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 00:39:05 +00:00
Jim Grosbach
734738d3bd Remove too-strict assertion. We may want the vreg copy of the physical register
to be of a different register class. For example, in Thumb1 if the live-in is
a high register, we want the vreg to be a low register. rdar://8224931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 23:48:02 +00:00
Devang Patel
5f2f69b648 Revert r109262.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109285 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 23:04:41 +00:00
Evan Cheng
3144687df7 - Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 22:39:59 +00:00
Dan Gohman
cd20c6fb18 Use the proper type for shift counts. This fixes a bootstrap error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 21:08:12 +00:00
Devang Patel
f83f42599d IF directory name is empty then try to extract one using absolute file name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 20:36:13 +00:00
Dan Gohman
a4f4d699ec DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
are not demanded. This often allows the anyext to be folded away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 18:03:30 +00:00
Dan Gohman
7c98283f0e Make SDNode::dump() print a newline at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109234 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 16:37:47 +00:00
Eric Christopher
54e1791e4b 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 01:05:59 +00:00
Chris Lattner
134d8eec87 remove the JIT "NeedsExactSize" feature and supporting logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:17:55 +00:00
Gabor Greif
481c4c0734 keep in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 17:18:03 +00:00
Gabor Greif
96f1d8ebdd mass elimination of reliance on automatic iterator dereferencing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 13:36:47 +00:00
Gabor Greif
a399781289 undo 80 column trespassing I caused
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 10:37:47 +00:00
Evan Cheng
89ba74d117 Re-apply r109079 with fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 06:24:48 +00:00
Owen Anderson
8b9177aee2 Revert r109079, which broke a lot of CodeGen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 06:01:28 +00:00
Reid Kleckner
c96a82a534 Initial modifications to MCAssembler and TargetMachine for the MCJIT.
Patch by Olivier Meurant!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109080 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 05:58:53 +00:00
Evan Cheng
a4081238aa Initialize RegLimit only when register pressure is being tracked.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109079 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 05:18:41 +00:00
Evan Cheng
4a863e2c75 More register pressure aware scheduling work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 23:53:58 +00:00
Jim Grosbach
917290043f For ARM/Darwin, add a dwarf entry indicating whether a function is arm or thumb
rdar://8202967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 23:03:52 +00:00
Owen Anderson
d13db2c59c Fix batch of converting RegisterPass<> to INTIALIZE_PASS().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109045 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 22:09:45 +00:00
Jim Grosbach
1e20b96313 80 column and trailing whitespace cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109037 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 21:21:52 +00:00
Dan Gohman
872814ae04 Disallow null as a named metadata operand.
Make MDNode::destroy private.
Fix the one thing that used MDNode::destroy, outside of MDNode itself.

One should never delete or destroy an MDNode explicitly. MDNodes
implicitly go away when there are no references to them (implementation
details aside).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 18:54:18 +00:00
Lang Hames
5a8ea65c5c Changed OStream templates to functions on raw_ostream, removed the unused "renderWarnings" function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109003 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 09:02:06 +00:00
Evan Cheng
4f6b4674be Teach bottom up pre-ra scheduler to track register pressure. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 06:09:07 +00:00
Jakob Stoklund Olesen
f2c6e367c1 Change the createSpiller interface to take a MachineFunctionPass argument.
The spillers can pluck the analyses they need from the pass reference.

Switch some never-null pointers to references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108969 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 23:50:15 +00:00
Jakob Stoklund Olesen
6a0dc079ef Implement loop splitting analysis.
Determine which loop exit blocks need a 'pre-exit' block inserted.
Recognize when this would be impossible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108941 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 21:46:58 +00:00
Dale Johannesen
21d35c1399 Fix test for switch statements and increase
threshold a bit per experimentation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 21:29:12 +00:00
Jakob Stoklund Olesen
abff28087f Appease the colonials.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 16:12:37 +00:00
Jakob Stoklund Olesen
8ae0263471 Beginning SplitKit - utility classes for live range splitting.
This is a work in progress. So far we have some basic loop analysis to help
determine where it is useful to split a live range around a loop.

The actual loop splitting code from Splitter.cpp is also going to move in here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108842 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 15:41:07 +00:00
Lang Hames
6089e464dd Updated css classes for the pressure table legend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108839 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 14:35:55 +00:00
Lang Hames
2725abd039 Oops - I tables render poorly in Chrome without this explicit height specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 10:29:46 +00:00
Lang Hames
f80f31eb9f Use run-length encoding to represent identical adjacent cells in the pressure
and interval table. Reduces output HTML file sizes by ~80% in my test cases.

Also fix access of private member type by << operator.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108823 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 10:18:54 +00:00
Lang Hames
245581b1ac Added support for turning HTML indentation on and off (indentation off by default).
Reduces output file size ~20% on my test cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108822 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 09:13:29 +00:00
Lang Hames
c4bcc778a8 Switched to rendering after allocation (but before rewriting) in PBQP.
Updated renderer to use allocation information from VirtRegMap (if
available) to render spilled intervals differently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 07:41:44 +00:00
Dale Johannesen
bf1ae5e254 Don't hoist things out of a large switch inside a
loop, for the reasons in the comments.  This is a
major win on 253.perlbmk on ARM Darwin.  I expect it
to be a good heuristic in general, but it's possible
some things will regress; I'll be watching.
7940152.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108792 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20 00:50:13 +00:00
Stuart Hastings
0db4271069 Correct line info for declarations/definitions. Radar 8063111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 23:56:30 +00:00
Devang Patel
58b8176ed3 Fix memory leak reported by valgrind.
Do not visit operands of old instruction. Visit all operands of new instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 23:25:39 +00:00
Dan Gohman
c6e59b71f5 After a custom inserter, in a block which has constant instructions,
update the current basic block in addition to the current insert
position, so that they remain consistent. This fixes rdar://8204072.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 22:48:56 +00:00
Evan Cheng
d70f57b254 ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 22:15:08 +00:00
Evan Cheng
46dcb57e18 Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64.
This property will be used by the register pressure tracking instruction scheduler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 18:47:01 +00:00