Commit Graph

12515 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
e17232ee4d Dont emit 'DBG_VALUE %noreg, ...' to terminate user variable ranges.
These ranges get completely jumbled by the post-ra scheduler, and it is not
really reasonable to expect it to make sense of them.

Instead, teach DwarfDebug to notice when user variables in registers are
clobbered, and terminate the ranges there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 00:21:41 +00:00
Dan Gohman
b55d6b6a7e Fix fast-isel address mode folding to avoid folding instructions
outside of the current basic block. This fixes PR9500, rdar://9156159.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128041 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-22 00:04:35 +00:00
Devang Patel
ffcb717488 Try again to make this test darwin only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128036 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 23:11:08 +00:00
Devang Patel
d9ee5c8b28 Force x86_64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 21:37:52 +00:00
Devang Patel
a796fa547f Enable this test only for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21 20:32:56 +00:00
Rafael Espindola
7c18fa87a4 Write the section table and the section data in the same order that
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-20 18:44:20 +00:00
Anders Carlsson
a201c4c2e6 Add an optimization to GlobalOpt that eliminates calls to __cxa_atexit, if the function passed is empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-20 17:59:11 +00:00
Daniel Dunbar
579967a7ec Disable test in a way that keeps lit happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-20 00:04:51 +00:00
Daniel Dunbar
7a90e04fc7 Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessors
to canonicalize IR", it broke a lot of things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 21:47:14 +00:00
Evan Cheng
ae16d6b972 SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IR
to have single return block (at least getting there) for optimizations. This
is general goodness but it would prevent some tailcall optimizations.
One specific case is code like this:
int f1(void);
int f2(void);
int f3(void);
int f4(void);
int f5(void);
int f6(void);
int foo(int x) {
  switch(x) {
  case 1: return f1();
  case 2: return f2();
  case 3: return f3();
  case 4: return f4();
  case 5: return f5();
  case 6: return f6();
  }
}

=>
LBB0_2:                                 ## %sw.bb
  callq   _f1
  popq    %rbp
  ret
LBB0_3:                                 ## %sw.bb1
  callq   _f2
  popq    %rbp
  ret
LBB0_4:                                 ## %sw.bb3
  callq   _f3
  popq    %rbp
  ret

This patch teaches codegenprep to duplicate returns when the return value
is a phi and where the phi operands are produced by tail calls followed by
an unconditional branch:

sw.bb7:                                           ; preds = %entry
  %call8 = tail call i32 @f5() nounwind
  br label %return
sw.bb9:                                           ; preds = %entry
  %call10 = tail call i32 @f6() nounwind
  br label %return
return:
  %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ]
  ret i32 %retval.0

This allows codegen to generate better code like this:

LBB0_2:                                 ## %sw.bb
        jmp     _f1                     ## TAILCALL
LBB0_3:                                 ## %sw.bb1
        jmp     _f2                     ## TAILCALL
LBB0_4:                                 ## %sw.bb3
        jmp     _f3                     ## TAILCALL

rdar://9147433


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 17:17:39 +00:00
Nadav Rotem
06cc324b9d Add support for legalizing UINT_TO_FP of vectors on platforms which do
not have native support for this operation (such as X86).
The legalized code uses two vector INT_TO_FP operations and is faster
than scalarizing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 13:09:10 +00:00
Stuart Hastings
9f24110280 Disable test to unbreak Linux. Radar 9156771.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127945 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 03:56:38 +00:00
Devang Patel
d847f4702a Test case for r127940.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127941 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 01:40:43 +00:00
Johnny Chen
94dad03a96 Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand.  Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 01:16:20 +00:00
Andrew Trick
f6325b9700 FileCheckize a test.
(one-by-one until valgrind is happy)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127925 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19 00:41:39 +00:00
Owen Anderson
0082830cb2 Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 22:50:18 +00:00
Evan Cheng
3f30af3f45 Match a few more obvious patterns to revsh. rdar://9147637.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127913 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 21:52:42 +00:00
Eli Friedman
b6192d2a9f Revert r127852; it's apparently causing an ICE on mingw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127909 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 21:12:29 +00:00
Justin Holewinski
8af78c9cf8 PTX: Fix various codegen issues
- Emit mad instead of mad.rn for shader model 1.0
- Emit explicit mov.u32 instructions for reading global variables
- (most PTX instructions cannot take global variable immediates)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 19:24:28 +00:00
Andrew Trick
5fd5b125ff Avoid creating canonical induction variables for non-native types.
For example, on 32-bit architecture, don't promote all uses of the IV
to 64-bits just because one use is a 64-bit cast.
Alternate implementation of the patch by Arnaud de Grandmaison.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 16:50:32 +00:00
Joerg Sonnenberger
96622aa063 Support explicit argument forms for the X86 string instructions.
For now, only the default segments are supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:59:40 +00:00
Che-Liang Chiou
8902ecb682 ptx: fix parameter order that is reversed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127874 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:23:56 +00:00
Che-Liang Chiou
88d3367baa ptx: add unconditional and conditional branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:08:52 +00:00
Eli Friedman
b4b8b0cc90 Add a target-specific branchless method for double-width relational
comparisons on x86.  Essentially, the way this works is that SUB+SBB sets
the relevant flags the same way a double-width CMP would.

This is a substantial improvement over the generic lowering in LLVM. The output
is also shorter than the gcc-generated output; I haven't done any detailed
benchmarking, though.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 02:34:11 +00:00
Eli Friedman
06caf2a66e FileCheck-ize and update test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127845 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 01:10:31 +00:00
Johnny Chen
5e5a40867a The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
Remove the offending logic and update the test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 00:38:03 +00:00
Devang Patel
813c9a0f19 Try to not lose variable's debug info during instcombine.
This is done by lowering dbg.declare intrinsic into dbg.value intrinsic.
Radar 9143931.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127834 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 22:18:16 +00:00
Johnny Chen
e68d8ec252 It used to be that t_addrmode_s4 was used for both:
o A8.6.195 STR (register) -- Encoding T1
o A8.6.193 STR (immediate, Thumb) -- Encoding T1

It has been changed so that now they use different addressing modes
and thus different MC representation (Operand Infos).  Modify the
disassembler to reflect the change, and add relevant tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 22:04:05 +00:00
Benjamin Kramer
1c10b8de46 BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied value by introducing an early shift.
This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into
	shrl	$2, %edi
	imulq	$613566757, %rdi, %rax
	shrq	$32, %rax
	ret

instead of
	movl    %edi, %eax
	imulq   $613566757, %rax, %rcx
	shrq    $32, %rcx
	subl    %ecx, %eax
	shrl    %eax
	addl    %ecx, %eax
	shrl    $4, %eax

on x86_64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 20:39:14 +00:00
Stuart Hastings
c74513d1b6 Reapply: Add type output to llvm-dis annotations. Patch by Yuri!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127824 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 19:50:04 +00:00
Richard Osborne
11bd0784d9 Add XCore intrinsic for setpsc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 18:42:05 +00:00
Daniel Dunbar
8d06ffca9b MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't have
been removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 16:25:24 +00:00
NAKAMURA Takumi
1aa7f7a997 test/CodeGen/X86/h-registers-1.ll: Add explicit -mtriple=x86_64-linux. It does not need to be checked on x86_64-win32 (aka Win64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127800 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 04:24:40 +00:00
Joerg Sonnenberger
d02c8b6cc1 Fix handling of @IDNTPOFF relocations, they need to get STT_TLS.
While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127780 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17 00:35:10 +00:00
NAKAMURA Takumi
ede4e28ca3 test/CodeGen/X86/constant-pool-remat-0.ll: FileCheck-ize and add explicit -mtriple=x86_64-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127775 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 23:01:31 +00:00
Cameron Zwarich
ebe8173941 The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.

This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 22:20:18 +00:00
Cameron Zwarich
7be4b7ed75 Rename a test to be more inclusive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127765 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 22:20:12 +00:00
Daniel Dunbar
83320a023c Revert r127757, "Patch to a fix dwarf relocation problem on ARM. One-line fix
plus the test where it used to break.", which broke Clang self-host of a
Debug+Asserts compiler, on OS X.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 22:16:39 +00:00
Richard Osborne
e17139b3e9 Add XCore intrinsics for setclk, setrdy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127761 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 21:56:00 +00:00
Renato Golin
2589d0aedf Patch to a fix dwarf relocation problem on ARM. One-line fix plus the test where it used to break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127757 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 21:05:52 +00:00
Cameron Zwarich
0a00615b34 Add a test for i1 zeroext arguments on x86-64. We currently generate code that
conforms to the ABI, but DAGCombine could in theory recognize the sequence of
zext asserts and truncates and generate incorrect code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 20:15:44 +00:00
Richard Osborne
bb057453db Add checkevent intrinsic to check if any resources owned by the current thread
can event.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127741 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 18:34:00 +00:00
NAKAMURA Takumi
bfc4c983a6 test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and x86_64-win32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127734 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:53:07 +00:00
NAKAMURA Takumi
37947c6bad test/CodeGen/X86: Add a pattern for Win64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127733 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:51 +00:00
NAKAMURA Takumi
ddbfbcf72e test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They are useless to Win64 target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127732 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:38 +00:00
NAKAMURA Takumi
4491aa49b3 test/CodeGen/X86/byval*.ll: Win64 has not supported byval yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127731 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:20 +00:00
NAKAMURA Takumi
67bf77e8fd test/CodeGen/X86/dyn-stackalloc.ll: FileCheck-ize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 13:52:08 +00:00
Cameron Zwarich
85b0f468cf Only convert allocas to scalars if it is profitable. The profitability metric I
chose is having a non-memcpy/memset use and being larger than any native integer
type. Originally I chose having an access of a size smaller than the total size
of the alloca, but this caused some minor issues on the spirit benchmark where
SRoA runs again after some inlining.

This fixes <rdar://problem/8613163>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127718 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:13:44 +00:00
Cameron Zwarich
0a0f6f342b Add native integer type TargetData to some existing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127717 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16 00:13:40 +00:00
Johnny Chen
276f6f9cf9 There were two issues fixed:
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 22:27:33 +00:00