6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-23 15:29:51 +00:00
Code Issues Projects Releases Wiki Activity
41,148 Commits 39 Branches 0 Tags 277 MiB
e3e3626338
Commit Graph

2775 Commits

Author SHA1 Message Date
Dale Johannesen
853244f8a6 Next limited float precision expansion (log2 12 bits) 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55866 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 23:49:37 +00:00
Owen Anderson
6e6074508c Revert r55859. This is breaking the build in the abscence of its companion commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55865 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 23:36:01 +00:00
Dan Gohman
8a11053f3c Move the code that inserts copies for function livein registers 
out of ScheduleDAGEmit.cpp and into SelectionDAGISel.cpp. This
allows it to be run exactly once per function, even if multiple
SelectionDAG iterations happen in the entry block, as may happen
with FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55863 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 22:59:21 +00:00
Dale Johannesen
852680a8fa Add the next limited-precision expansion. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55856 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 21:27:19 +00:00
Dan Gohman
638c6830c6 FastISel support for AND and OR with type i1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55846 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 18:44:22 +00:00
Dale Johannesen
59e577f73c Add hooks for other intrinsics to get low-precision expansions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55845 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 18:38:42 +00:00
Dan Gohman
40b189e4e2 FastISel support for ConstantExprs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55843 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 18:18:20 +00:00
Dan Gohman
be0034e3c2 Revert r55817. It broke PIC. FastISel will need to find a different 
approach here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55842 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 18:13:01 +00:00
Evan Cheng
c89d2feb35 Add a variant of AnalyzeCallOperands that can be used by fast isel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55838 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 16:59:26 +00:00
Duncan Sands
1c11debc94 "Fix" PR2762. The testcase now crashes codegen 
elsewhere due to a missing pattern for
v2f64 = sint_to_fp v2i32.  That is PR2687.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55828 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 08:13:35 +00:00
Dan Gohman
3dd168d445 Fix a search+replace-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55824 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 01:58:21 +00:00
Dale Johannesen
601d3c0145 Add -flimit-float-precision to enable some faster, 
but less accurate (non-IEEE) code sequences for
certain math library functions.  Add the first of
several such expansions.  Don't worry, if you don't
turn it on it won't affect you.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55823 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 01:48:15 +00:00
Dan Gohman
087c8507e5 FastISel support for unreachable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55818 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 01:08:41 +00:00
Dan Gohman
c7f4a8a80c In FastISel mode, the scheduler may be invoked multiple times 
in the same block. Fix the entry-block handling to only run at
at the beginning of the entry block, and not any other times.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55817 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 01:07:48 +00:00
Owen Anderson
95267a1e67 Add initial support for selecting constant materializations that require constant 
pool loads on X86 in fast isel.  This isn't actually used yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55814 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-05 00:06:23 +00:00
Dan Gohman
5b2298005d Add an include of SmallSet.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55793 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 20:49:27 +00:00
Dan Gohman
ae73dc1448 Tidy up several unbeseeming casts from pointer to intptr_t. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55779 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 17:05:41 +00:00
Dan Gohman
6448d91ad1 Clean up uses of TargetLowering::getTargetMachine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 15:39:15 +00:00
Dale Johannesen
7794f2a3a7 Add intrinsics for log, log2, log10, exp, exp2. 
No functional change (and no FE change to generate them).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55753 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-04 00:47:13 +00:00
Dan Gohman
104e4ce162 Do trivial local CSE for constants and other non-Instruction values 
in FastISel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55748 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 23:32:19 +00:00
Dan Gohman
2a7c671e2e Put RegsForValue in the llvm namespace to avoid warnings about 
classes in the llvm namespace having members with types from
anonymous namespaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55747 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 23:18:39 +00:00
Dan Gohman
3df24e667f Create HandlePHINodesInSuccessorBlocksFast, a version of 
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.

This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55746 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 23:12:08 +00:00
Owen Anderson
d5d81a457b Oops, I accidentally broke the fallback case with my last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55704 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 17:51:57 +00:00
Owen Anderson
99aaf108cd Fix an issue where we were reusing materializations of constants in blocks not dominated by the materialization. This is 
the simple fix, materializing the constant before every use.  It might be better to either track domination of uses or
to materialize all constants and the beginning of the function and let remat sort when to do materialization at uses.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55703 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 17:37:03 +00:00
Dan Gohman
f0cbcd4880 Split the SelectionDAG-building code, including the FunctionLoweringInfo 
and SelectionDAGLowering classes, out of SelectionDAGISel.cpp and put
it in a separate file, SelectionDAGBuild.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55701 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 16:12:24 +00:00
Dan Gohman
94b8d7ea63 Separate MachineInstr-emitting routines from actual scheduling 
routines and move them into a separate file, ScheduleDAGEmit.cpp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55699 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 16:01:59 +00:00
Evan Cheng
f45261fb9b If TargetSelectInstruction returns true, move to next instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55692 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-03 06:43:41 +00:00
Evan Cheng
36fd941fc0 80 col violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55668 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-02 21:59:13 +00:00
Dan Gohman
d2ff647964 Ensure that HandlePHINodesInSuccessorBlocks is run for all blocks, 
even in FastISel mode in the case where FastISel successfully 
selects all the instructions. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55641 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-02 20:17:56 +00:00
Gabor Greif
ed63214fcb Provide two overloads of AnalyzeNewNode. 
The first can update the SDNode in an SDValue
while the second is called with SDNode* and
returns a possibly updated SDNode*.

This patch has no intended functional impact,
but helps eliminating ugly temporary SDValues.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55608 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 15:10:19 +00:00
Duncan Sands
1189f3ac3b Even though no caller actually uses the new value 
(what matters is that it is added to the worklist),
it seems more logical to return it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55606 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-09-01 13:11:13 +00:00
Bill Wendling
2692d59574 Another situation where ROTR is cheaper than ROTL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55577 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 01:13:31 +00:00
Bill Wendling
353dea2f0a For this pattern, ROTR is the cheaper option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55576 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 01:04:56 +00:00
Bill Wendling
c5cbda12e9 - Fix comment so that it describes how the code really works: 
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotl x, y)
   // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
   //   (rotr x, (sub 32, y))

Example: (x == 0xDEADBEEF and y == 4)

    (x << 4) | (x >> 28)
 => 0xEADBEEF0 | 0x0000000D
 => 0xEADBEEFD

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => 0xEADBEEFD

- Fix comment and code for second version. It wasn't using the rot* propertly.

   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 
   //   (rotr x, y)
   // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
   //   (rotl x, (sub 32, y))

    (x << 28) | (x >> 4)
 => 0xD0000000 | 0x0DEADBEE
 => 0xDDEADBEE

    (rotl x, 4)
 => 0xEADBEEFD

    (rotr x, 28)
 => (0xEADBEEFD)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55575 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-31 00:37:27 +00:00
Gabor Greif
dc71563794 typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55574 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 22:16:05 +00:00
Gabor Greif
12632d2222 fix some 80-col violations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55571 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 19:29:20 +00:00
Evan Cheng
eb9f89287e Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 02:03:58 +00:00
Owen Anderson
cc54e76cc6 Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg 
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-30 00:38:46 +00:00
Evan Cheng
4529966d99 Fix 80 col. violations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55551 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 23:20:46 +00:00
Evan Cheng
17a568b668 Back out 55498. It broken Apple style bootstrapping. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55549 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-29 22:21:44 +00:00
Dan Gohman
99b218218c Add a target callback for FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 23:21:34 +00:00
Gabor Greif
ba36cb5242 erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:40:38 +00:00
Dan Gohman
205d92589b Implement null and undef values for FastISel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55500 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:19:07 +00:00
Dan Gohman
a3f8b7a4ce Optimize DAGCombiner's worklist processing. Previously it started 
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55498 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 21:01:56 +00:00
Dan Gohman
9ffd8b5720 Move CaseBlock, JumpTable, and BitTestBlock to be members of 
SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55497 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 20:38:18 +00:00
Dan Gohman
5edd361497 Fix a FastISel bug where the instructions from lowering the arguments 
were being emitted after the first instructions of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55496 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 20:28:56 +00:00
Rafael Espindola
91ee5454ae Reduce the size of the Parts vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55483 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 18:29:58 +00:00
Owen Anderson
c0bb68b982 Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55482 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 18:26:01 +00:00
Owen Anderson
40a468f249 FastEmitInst_extractsubreg doesn't need to be passed the register class. It can get it from MachineRegisterInfo instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55476 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 17:47:37 +00:00
Rafael Espindola
c748ffa4e4 Correctly resize the Parts array. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55471 91177308-0d34-0410-b5e6-96231b3b80d8
 2008-08-28 14:24:45 +00:00