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eb8eac6be2
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376 Commits

Author SHA1 Message Date
Matt Arsenault
eb8eac6be2 Make isSetCCEquivalent respect the TargetBooleanContents 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205336 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-01 18:13:26 +00:00
Matt Arsenault
193c3e91b9 R600: Compute masked bits for min and max 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205242 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 19:35:33 +00:00
Matt Arsenault
828bfc7350 R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205236 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 18:21:18 +00:00
Tom Stellard
1f143aa3e9 R600/SI: Lower i64 SELECT by bitcasting to a vector type 
This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered
using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205187 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-31 14:01:55 +00:00
Matt Arsenault
0c6d96cf16 R600: Implement isZExtFree. 
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204946 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-27 17:23:31 +00:00
Matt Arsenault
94687c0f43 R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204945 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-27 17:23:24 +00:00
Matt Arsenault
e0e503801f R600: Add a testcase for sext_in_reg I missed. 
This sext_inreg i32 in i64 case was already handled, but not enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204840 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-26 18:31:06 +00:00
Matt Arsenault
0227461758 R600: Add failing testcase for <3 x i32> stores. 
This is supposed to have the same store size and alignment as <4 x i32>,
but currently is split into a 64-bit and 32-bit store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204729 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-25 16:50:55 +00:00
Matt Arsenault
add2e2ec8f R600/SI: Fix extra mov from legalizing 64-bit SALU ops. 
Check the register class of each operand individually
to avoid an extra copy to a vgpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204662 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 20:08:13 +00:00
Matt Arsenault
3a96e61469 R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops. 
No longer asserts, but now you get moves loading legal immediates
into the split 32-bit operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204661 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 20:08:09 +00:00
Matt Arsenault
db1807144a R600/SI: Fix 64-bit bit ops that require the VALU. 
Try to match scalar and first like the other instructions.
Expand 64-bit ands to a pair of 32-bit ands since that is not
available on the VALU.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204660 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 20:08:05 +00:00
Matt Arsenault
6c199d8212 R600: Implement isNarrowingProfitable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204658 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 19:43:31 +00:00
Matt Arsenault
875870fdb4 R600/SI: Fix 64-bit private loads. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204630 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 17:50:46 +00:00
Matt Arsenault
55d17f4842 R600/SI: Move instruction patterns to scalar versions. 
Some of them also had the pattern on both, so this removes the
duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204492 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-21 18:01:18 +00:00
Tom Stellard
a1d28f6dd7 R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204476 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-21 15:51:57 +00:00
Tom Stellard
1f1c0495d0 R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204475 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-21 15:51:54 +00:00
Matt Arsenault
e3620da269 R600/SI: Add support for 64-bit LDS writes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204274 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-19 22:19:54 +00:00
Matt Arsenault
62b3e22092 R600/SI: Add support for 64-bit LDS loads. 
v2:
  -Use correct opcode for DS_READ_64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204273 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-19 22:19:52 +00:00
Matt Arsenault
6eaa49233f R600/SI: Match i16 immediate offset of LDS instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204272 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-19 22:19:49 +00:00
Matt Arsenault
adf5141ecd R600/SI: Fix test checking wrong instruction operand. 
The source and destination happen to be the same register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204271 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-19 22:19:45 +00:00
Matt Arsenault
9c0b2d08d3 R600/SI: Don't display the GDS bit. 
It isn't actually used now, and probably never will be, plus it makes
tests less annoying. I also think SC prints GDS instructions as a
separate instruction name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204270 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-19 22:19:43 +00:00
NAKAMURA Takumi
3bdef4b6dc CodeGen/R600/v_cndmask.ll: Relax an expression to unbreak msvcrt. 
V_CNDMASK_B32_e64 v0, v0, -1.#QNAN0e+00, s[2:3], 0, 0, 0, 0

FIXME: We really need to implement our formatter...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204118 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-18 06:17:22 +00:00
Kevin Enderby
c153e49aa9 Making a guess to fix the test case with r204056 to get the build bot working. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204073 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 19:00:03 +00:00
Matt Arsenault
2683baa8ac R600: Match sign_extend_inreg to BFE instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204072 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 18:58:11 +00:00
Tom Stellard
ad52f4f70c R600/SI: Fix implementation of isInlineConstant() used by the verifier 
The type of the immediates should not matter as long as the encoding is
equivalent to the encoding of one of the legal inline constants.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204056 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 17:03:52 +00:00
Tom Stellard
eb7876083d R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 
This instructions writes to an 32-bit SGPR.  This change required adding
the 32-bit VCC_LO and VCC_HI registers, because the full VCC register
is 64 bits.

This fixes verifier errors on several of the indirect addressing piglit
tests.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204055 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 17:03:51 +00:00
Tom Stellard
47feea0802 R600: LDS instructions shouldn't implicitly define OQAP 
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.

This fixes a hang in the opencv MedianFilter tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203818 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-13 17:13:04 +00:00
Matt Arsenault
054f4eccd2 R600: Fix trunc store from i64 to i1 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203695 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-12 18:45:52 +00:00
Tom Stellard
6cadd406cc R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203281 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-07 20:12:39 +00:00
Tom Stellard
7e06370873 R600/SI: Custom lower i1 stores 
These are sometimes created by the shrink to boolean optimization in the
globalopt pass.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203280 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-07 20:12:33 +00:00
Matt Arsenault
161e3a80b2 R600: Fix extloads from i8 / i16 to i64. 
This appears to only be working for global loads. Private
and local break for other reasons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203135 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 17:34:12 +00:00
Matt Arsenault
b4cd160bb9 R600/SI: Expand selects on vectors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203134 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-06 17:34:03 +00:00
Matt Arsenault
c59a9f09fb R600: Add failing control flow tests. 
Simple cases hit a variety of problems at -O0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202601 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-01 21:45:41 +00:00
Tom Stellard
9f0d68f522 R600/SI: Expand all v16[if]32 operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202543 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-28 21:36:37 +00:00
Michel Danzer
644aecfc97 R600/SI: Optimize SI_KILL for constant operands 
If the SI_KILL operand is constant, we can either clear the exec mask if
the operand is negative, or do nothing otherwise.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202337 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-27 01:47:09 +00:00
Michel Danzer
a5fbf24716 R600/SI: Allow SI_KILL for geometry shaders 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202336 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-27 01:47:02 +00:00
Tom Stellard
d8c31046a9 R600/SI: Custom select 64-bit ADD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202194 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-25 21:36:18 +00:00
Matt Arsenault
bc247e4afd R600/SI - Add new CI arithmetic instructions. 
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202077 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-24 21:01:28 +00:00
Quentin Colombet
a6e734d2ed [CodeGenPrepare] Fix the check of the legality of an instruction. 
The API expects an ISD opcode, not an IR opcode.
Fixes a regression for R600.

Related to <rdar://problem/15519855>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201923 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-22 01:06:41 +00:00
Nico Rieck
1800766f5a Fix more broken CHECK lines 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201493 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-16 13:28:39 +00:00
Quentin Colombet
038600b42e [CodeGenPrepare][AddressingModeMatcher] Give up on type promotion if the 
transformation does not bring any immediate benefits and introduce an illegal
operation. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201439 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-14 22:23:22 +00:00
Tom Stellard
5f80594797 TargetLowering: n * r where n > 2 should be an illegal addressing mode 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201433 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-14 21:10:34 +00:00
Tom Stellard
0f2e653317 R600/SI: Expand all v8[if]32 operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201371 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 23:34:15 +00:00
Tom Stellard
9757ba1206 R600/SI: Add a pattern for i32 anyext 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201370 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 23:34:13 +00:00
Tom Stellard
130f271259 R600/SI: Completely Disable TypeRewriter on compute 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201369 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 23:34:12 +00:00
Tom Stellard
1a52c2b25a R600/SI: Split global vector loads with more than 4 elements 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201368 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 23:34:10 +00:00
Tom Stellard
c4fea3594f R600/SI: Add ShaderType attribute to some tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201367 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-13 23:34:07 +00:00
Matt Arsenault
69bc4ddf10 R600/SI: Fix assertion on infinite loops. 
This isn't the most useful case to fix in the real world,
but bugpoint runs into this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201177 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-11 21:12:38 +00:00
Tom Stellard
42faffddb9 R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are used 
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0.  When M0 is uninitialized,
then we experience undefined behavior.

This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201097 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-10 16:58:30 +00:00
Matt Arsenault
26bc2c8eed R600/SI: Add failing test for 3 x i64 vectors. 
Stores of <4 x i64> do work (although they do expand to 4 stores
instead of 2), but 3 x i64 vectors fail to select.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200989 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-07 20:29:40 +00:00