Daniel Dunbar
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fe09b2098a
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Twines: Don't allow implicit conversion from integers, this is too tricky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77605 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-30 17:37:43 +00:00 |
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Daniel Dunbar
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0e2771f4c4
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Match X86 register names to number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77404 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-29 00:02:19 +00:00 |
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Daniel Dunbar
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22be5225ff
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tblgen/AsmMatcher: Emit simple matcher for register names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76212 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-17 18:51:11 +00:00 |
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Daniel Dunbar
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d51ffcf303
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Stub out assembly matcher (.s -> MCInst) tblgen backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75378 91177308-0d34-0410-b5e6-96231b3b80d8
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2009-07-11 19:39:44 +00:00 |
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