exception handling. Also fix an extra underscore typo in one instance of
"__ARM_EABI__". Radar 8236264.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109451 91177308-0d34-0410-b5e6-96231b3b80d8
we are using AVX and no AVX version of the desired intruction is present,
this is better for incremental dev (without fallbacks it's easier to spot
what's missing). Not sure this is the best hack thought (we can also disable
all HasSSE* predicates by dinamically marking them 'false' if AVX is present)
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This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716
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it inserted rather than using LoopInfo::getCanonicalInductionVariable to
rediscover it, since that doesn't work on non-canonical loops. This fixes
infinite recurrsion on such loops; PR7562.
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dependence on DominanceFrontier. Instead, add an explicit DominanceFrontier
pass in StandardPasses.h to ensure that it gets scheduled at the right
time.
Declare that loop unrolling preserves ScalarEvolution, and shuffle some
getAnalysisUsages.
This eliminates one LoopSimplify and one LCCSA run in the standard
compile opts sequence.
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don't visit all blocks in the function, and don't iterate over the split blocks'
predecessor lists for each block visited.
Also, remove the special-case test for the entry block. Splitting the entry
block isn't common enough to make this worthwhile.
This fixes a major compile-time bottleneck which is exposed now that
LoopSimplify isn't being redundantly run both before and after
DominanceFrontier.
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hanging off a value, then the dropping code will intentionally not drop
it too (since this is almost certainly a bug).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109337 91177308-0d34-0410-b5e6-96231b3b80d8
instead of fixed size arrays, so that increasing FirstVirtualRegister to 16K
won't cause a compile time performance regression.
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appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.
On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.
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function live in set. This will give us tGPR for Thumb1 and GPR otherwise,
so the copy will be spillable. rdar://8224931
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to be of a different register class. For example, in Thumb1 if the live-in is
a high register, we want the vreg to be a low register. rdar://8224931
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