6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-02 07:11:49 +00:00
Code Issues Projects Releases Wiki Activity
92,651 Commits 39 Branches 0 Tags 277 MiB
f3d6e32c09
Commit Graph

92651 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Vincent Lejeune
f3d6e32c09 R600: Add a pass that merge Vector Register 
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 21:38:04 +00:00
Sean Silva
f41d317054 [docs] Add link to C++ ABI document. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183342 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 21:11:16 +00:00
Sean Silva
c85756f4b0 [docs] Add link to SysV ABI document. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183341 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 21:11:11 +00:00
Sean Silva
d56d756611 [ELF] Add ELFOSABI_GNU. 
ELFOSABI_LINUX is a historical alias for ELFOSABI_GNU according to
<http://www.sco.com/developers/gabi/latest/ch4.eheader.html>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183339 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 20:55:58 +00:00
Rafael Espindola
c9f2cc7e05 Don't hide the first ELF symbol. 
The first symbol on ELF is dummy, but it has a defined content and readelf
normally displays it. With this change llvm-readobj also displays it and we
can check that llvm-mc output is correct according to the standard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183337 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 20:33:54 +00:00
Vincent Lejeune
512119770e R600: Schedule copy from phys register at beginning of block 
It allows regalloc pass to remove them by trivially assigning associated reg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 20:27:35 +00:00
Sean Silva
6ed30e0f0c yaml2obj: split out COFF logic into separate file 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183335 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 19:56:47 +00:00
Akira Hatanaka
8270e68c56 [mips] brcond + setgt/setugt instruction selection patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 19:49:55 +00:00
Sean Silva
db9dc53871 yaml2obj: add -format=<fmt> to choose input YAML interpretation 
See the comment in yaml2obj.cpp for why this is currently needed.
Eventually we can get rid of this, but for now it is needed in order to
make forward progress with adding ELF support, and should be
straightforward to remove later.

Also, preserve the default of COFF, to avoid breaking existing tests.
This policy can easily be changed later though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183332 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 18:51:34 +00:00
Jakub Staszak
cc81b38c4c Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183328 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 18:27:02 +00:00
Michael Liao
9a508ef64a [PATCH] Fix VGATHER* operand constraints 
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 18:12:26 +00:00
Rafael Espindola
bcb1ea8ef6 Represent symbols with a SymbolIndex,SectionIndex pair. 
With this patch we use the SectionIndex directly, instead of counting the
number of symbol tables. This saves a DenseMap lookup every time we want to
find which symbol a relocation refers to.

Also simplify based on the fact that there is at most one SHT_SYMTAB and one
SHT_DYNSYM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183326 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 17:54:19 +00:00
Arnold Schwaighofer
31588f3005 ARM sched model: Add more ALU and CMP instructions 
Reapply of 183258.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183321 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 16:36:51 +00:00
Arnold Schwaighofer
c82157378e ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

Reapply of r183257. (Removed empty InstRW for division on swift)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183319 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 16:06:11 +00:00
Arnold Schwaighofer
d87bd5627e ARMInstrInfo: Improve isSwiftFastImmShift 
An instruction with less than 3 inputs is trivially a fast immediate shift.

Reapply of 183256, should not have caused the tablegen segfault on linux either.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183314 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 14:59:36 +00:00
Arnold Schwaighofer
fcce70ad52 SubtargetEmitter fix 
Don't output data if we are supposed to ignore the record.

Reapply of 183255, I don't think this was causing the tablegen segfault on linux
testers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183311 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 14:06:50 +00:00
Mihai Popa
2248cf5906 This is a simple patch that changes RRX and RRXS to accept all registers as operands. 
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 13:23:51 +00:00
Sylvestre Ledru
7e129466d8 The GNU/HURD is also using the libc. Therefor, endian.h should be included, not machine/endian.h. See full build log https://buildd.debian.org/status/fetch.php?pkg=llvm-toolchain-3.3&arch=hurd-i386&ver=1%3A3.3~%2Brc3-1~exp1&stamp=1370358869 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183303 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 09:17:26 +00:00
Andrew Trick
d7aad34bcb Fix a tblgen subtargetemitter bug, for future Swift support. 
This fixes some of the ridiculously complex code for optimizing the
machine model tables that are shared among all processors of a given
target. A9 and Swift both use the "special" feature that maps old
itinerary classes to new machine model defs. They map different
overlapping subsets of instructions, which wasn't handled correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183302 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 06:55:20 +00:00
David Blaikie
032d62487c PR15662: Optimized debug info produces out of order function parameters 
When a function is inlined we lazily construct the variables
representing the function's parameters. After that, we add any remaining
unused parameters.

If the function doesn't use all the parameters, or uses them out of
order, then the DWARF would produce them in that order, producing a
parameter order that doesn't match the source.

This fix causes us to always keep the arg variables at the start of the
variable list & in the original order from the source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183297 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 05:39:59 +00:00
Tom Stellard
ad7ecc65b1 R600: Make sure to schedule AR register uses and defs in the same clause 
Reviewed-by: vljn at ovi.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 03:43:06 +00:00
Rafael Espindola
23a22cdedd Don't print default values for NumberOfAuxSymbols and AuxiliaryData. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183293 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 03:20:13 +00:00
Rafael Espindola
0962b1683f Handle (at least don't crash on) relocations with no symbols. 
Should fix the MCJIT tests on PPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183288 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 02:55:01 +00:00
Rafael Espindola
5fd5fe0f7b Move BinaryRef to a new include/llvm/Object/YAML.h file. 
It will be used for ELF dumping too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183287 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 02:32:26 +00:00
Rafael Espindola
6afb65c2b7 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 01:48:30 +00:00
Rafael Espindola
6c1202c459 Handle relocations that don't point to symbols. 
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-05 01:33:53 +00:00
Sean Silva
cc5a6cb0a2 [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro 
LLVM_YAML_STRONG_TYPEDEF() is the correct macro to perform this function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183280 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:36:41 +00:00
Vincent Lejeune
bbbdba891b R600: Add a pass that merge Vector Register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d R600: Const/Neg/Abs can be folded to dot4 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 23:17:15 +00:00
Evan Cheng
00ed010d9e Cortex-R5 can issue Thumb2 integer division instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:52:09 +00:00
Arnold Schwaighofer
8a227084a5 Revert series of sched model patches until I figure out what is going on. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
f500aa0b24 ARM sched model: Add VFP div instruction on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:08 +00:00
Arnold Schwaighofer
858f6f8899 ARM sched model: Add SIMD/VFP load/store instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183270 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:07 +00:00
Arnold Schwaighofer
e52041c16e ARM sched model: Add integer VFP/SIMD instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183269 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:05 +00:00
Arnold Schwaighofer
f3a2329d33 ARM sched model: Add integer load/store instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:04 +00:00
Arnold Schwaighofer
755d1295a5 ARM sched model: Add integer arithmetic instructions on Swift 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183267 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:02 +00:00
Arnold Schwaighofer
eb9948e781 ARM sched model: Cortex A9 - More InstRW sched resources 
Add more InstRW mappings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183266 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:16:00 +00:00
Arnold Schwaighofer
002faf20a7 ARM sched model: Add branch thumb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:59 +00:00
Arnold Schwaighofer
16d915018b ARM sched model: Add branch thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183264 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:57 +00:00
Arnold Schwaighofer
36ea791280 ARM sched model: Add branch instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:56 +00:00
Arnold Schwaighofer
fdbca2faac ARM sched model: Add preload thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183262 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:54 +00:00
Arnold Schwaighofer
d3b8445d14 ARM sched model: Add preload instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183261 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:52 +00:00
Arnold Schwaighofer
23cb39a3d9 ARM sched model: Add more ALU and CMP thumb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183260 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:51 +00:00
Arnold Schwaighofer
1942e3254d ARM sched model: Add more ALU and CMP thumb2 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183259 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:49 +00:00
Arnold Schwaighofer
4c53731e5b ARM sched model: Add more ALU and CMP instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183258 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:47 +00:00
Arnold Schwaighofer
611c6e1359 ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:46 +00:00
Arnold Schwaighofer
ede7eeae32 ARMInstrInfo: Improve isSwiftFastImmShift 
An instruction with less than 3 inputs is trivially a fast immediate shift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183256 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:43 +00:00
Arnold Schwaighofer
54d63ccdb7 SubtargetEmitter fix 
Don't output data if we are supposed to ignore the record.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183255 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 22:15:41 +00:00
Richard Smith
2b18526696 Fix link. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183248 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 20:42:42 +00:00
Venkatraman Govindaraju
1e06bcbd63 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-04 18:33:25 +00:00