Commit Graph

33 Commits

Author SHA1 Message Date
Craig Topper
a0ec3f9b7b Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-14 04:42:23 +00:00
Andrew Trick
a3d82ce19f Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-15 04:50:06 +00:00
Benjamin Kramer
aca93cf44f tblgen: Assert that InstRWs doesn't grows when we don't expect it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183690 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-10 20:19:35 +00:00
Benjamin Kramer
068ecc15c0 tblgen: always lookup values from the original vector as it could be grown under our feet.
PR16281.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183630 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-09 15:20:23 +00:00
Arnold Schwaighofer
0efc78257b CodeGenSchedule: Use resize instead of copying a vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 00:04:30 +00:00
Arnold Schwaighofer
45dc03287e CodeGenSchedule: smallvector.push_back(smallvector[0]) is dangerous
The element passed to push_back is not copied before the vector reallocates.
The client needs to copy the element first before passing it to push_back.

No test case, will be tested by follow-up swift scheduler model change (it
segfaults without this change).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183459 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 23:23:14 +00:00
Andrew Trick
d7aad34bcb Fix a tblgen subtargetemitter bug, for future Swift support.
This fixes some of the ridiculously complex code for optimizing the
machine model tables that are shared among all processors of a given
target. A9 and Swift both use the "special" feature that maps old
itinerary classes to new machine model defs. They map different
overlapping subsets of instructions, which wasn't handled correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183302 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 06:55:20 +00:00
Andrew Trick
e30f32a69b Machine model: verify well-formed processor resource groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-23 23:45:14 +00:00
Andrew Trick
bc4de7cec1 Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 19:08:31 +00:00
Dan Gohman
1cbd401756 Revert r178166. According to Howard, this code is actually ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178319 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-29 00:13:08 +00:00
Dan Gohman
dcdc0faf59 Avoid undefined behavior from passing a std::vector's own contents
in as an argument to push_back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178166 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-27 18:44:56 +00:00
Andrew Trick
82e7c4f533 TableGen SubtargetEmitter fix to allow A9 and Swift to coexist.
Allow variants to be defined only for some processors on a target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 21:36:39 +00:00
Andrew Trick
02fec34de1 TableGen fix for the new machine model.
Properly handle cases where a group of instructions have different
SchedRW lists with the same itinerary class.
This was supposed to work, but I left in an early break.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-18 20:42:25 +00:00
Andrew Trick
1ab961f6d3 Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-16 18:58:55 +00:00
Jakob Stoklund Olesen
64110ffc9e Add SchedRW as an Instruction field.
Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {
    ...
  }

Which is now possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-15 22:51:13 +00:00
Andrew Trick
1754aca83a MachineModel: Add a ProcResGroup class.
This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a
SuperUnit.

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-14 21:21:50 +00:00
Andrew Trick
d9a4f0cbd2 MachineModel: Inconsequential TableGen SubtargetEmitter fix.
Drive by fix. I noticed some missing logic that might bite future
users. This shouldn't affect the final output on currently modeled
targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174142 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-01 03:19:54 +00:00
Chandler Carruth
4ffd89fa4d Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04 10:37:14 +00:00
Rafael Espindola
322ff88345 Fix a build problem with xlc. The error message was
"../llvm-git/utils/TableGen/CodeGenSchedule.cpp", line 1594.12: 1540-0218 (S) The call does not match any parameter list for "operator+".
"../llvm-git/include/llvm/ADT/STLExtras.h", line 130.1: 1540-1283 (I) "template <class _Iterator, class Func> llvm::operator+(mapped_iterator<_Iterator,Func>::difference_type, const mapped_iterator<_Iterator,Func> &)" is not a viable candidate.

Patch by Kai.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-02 20:57:36 +00:00
Joerg Sonnenberger
61131ab15f Remove exception handling usage from tblgen.
Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25 20:33:17 +00:00
Joerg Sonnenberger
2c6d71388f Don't use stack unwinding to provide the location information for
SetTheory, but pass down the location explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24 22:03:59 +00:00
Sean Silva
6cfc806a6b tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.
Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 20:24:43 +00:00
Andrew Trick
dbe6d43dfa TableGen subtarget emitter cleanup.
Consistently evaluate Aliases and Sequences recursively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165604 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10 05:43:13 +00:00
Andrew Trick
13745262a8 Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 23:06:32 +00:00
Andrew Trick
2062b1260f TableGen subtarget emitter, nearly first class support for SchedAlias.
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165179 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 23:06:28 +00:00
Andrew Trick
fe05d98c25 Cleanup TableGen subtarget emitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165178 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03 23:06:25 +00:00
Andrew Trick
9264988311 Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22 02:24:21 +00:00
Andrew Trick
3b8fb648c6 SchedMachineModel: compress the CPU's WriteLatencyTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 04:43:19 +00:00
Andrew Trick
bc4ff6e3cf TableGen subtarget parser: Add getProcResourcesIdx().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:43 +00:00
Andrew Trick
3cbd1786ac TableGen subtarget parser. Handle new machine model.
Collect processor resources from the subtarget defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 00:20:02 +00:00
Andrew Trick
5e613c260b TableGen subtarget parser. Handle new machine model.
Infer SchedClasses from variants defined by the target or subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 00:19:59 +00:00
Andrew Trick
48605c3406 TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 00:19:57 +00:00
Andrew Trick
2661b411cc I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 04:00:00 +00:00