Commit Graph

19498 Commits

Author SHA1 Message Date
Quentin Colombet
fcca6c690c Teach AsmPrinter how to print odd constants.
Fix an assertion when the compiler encounters big constants whose bit width is
not a multiple of 64-bits.
Although clang would never generate something like this, the backend should be
able to handle any legal IR.

<rdar://problem/13363576>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 18:36:03 +00:00
Roman Divacky
6ca5fd3f30 Fix a typo in asm string of BP* family of instructions. With this fix
I am able to compile/assemble/link/run /bin/echo from FreeBSD.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183537 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 17:46:57 +00:00
Rafael Espindola
62ed8d3e35 Support OpenBSD's native frame protection conventions.
OpenBSD's stack smashing protection differs slightly from other
platforms:

  1. The smash handler function is "__stack_smash_handler(const char
     *funcname)" instead of "__stack_chk_fail(void)".

  2. There's a hidden "long __guard_local" object that gets linked
     into each executable and DSO.

Patch by Matthew Dempsky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183533 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 16:35:57 +00:00
Michael Gottesman
9eb856bc29 [objc-arc] Ensure that the cfg path count does not overflow when we multiply TopDownPathCount/BottomUpPathCount.
rdar://12480535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183489 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 06:16:49 +00:00
Venkatraman Govindaraju
01021a8b93 [Sparc]: Use cmp instruction instead of subcc to compare integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 00:03:36 +00:00
Kevin Enderby
285bd8e6f9 Move the test for the data in code into the ARM directory as it is an ARM
binary that is used for the test.  Caught by Jim Grosbach!

rdar://11791371


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 20:28:28 +00:00
Rafael Espindola
ab9ba5321d Add a testcase from pr16244.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 19:15:23 +00:00
Kevin Enderby
54154f3bf1 Teach llvm-objdump with the -macho parser how to use the data in code table
from the LC_DATA_IN_CODE load command.  And when disassembling print
the data in code formatted for the kind of data it and not disassemble those
bytes.

I added the format specific functionality to the derived class MachOObjectFile
since these tables only appears in Mach-O object files. This is my first
attempt to modify the libObject stuff so if folks have better suggestions
how to fit this in or suggestions on the implementation please let me know.

rdar://11791371


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 17:20:50 +00:00
Rafael Espindola
e3a0e7f29d Print symbol names in relocations when dumping COFF as YAML.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-06 13:06:17 +00:00
Vincent Lejeune
f3d6e32c09 R600: Add a pass that merge Vector Register
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 21:38:04 +00:00
Rafael Espindola
c9f2cc7e05 Don't hide the first ELF symbol.
The first symbol on ELF is dummy, but it has a defined content and readelf
normally displays it. With this change llvm-readobj also displays it and we
can check that llvm-mc output is correct according to the standard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 20:33:54 +00:00
Vincent Lejeune
512119770e R600: Schedule copy from phys register at beginning of block
It allows regalloc pass to remove them by trivially assigning associated reg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 20:27:35 +00:00
Akira Hatanaka
8270e68c56 [mips] brcond + setgt/setugt instruction selection patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 19:49:55 +00:00
Michael Liao
9a508ef64a [PATCH] Fix VGATHER* operand constraints
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 18:12:26 +00:00
Mihai Popa
2248cf5906 This is a simple patch that changes RRX and RRXS to accept all registers as operands.
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183307 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 13:23:51 +00:00
David Blaikie
032d62487c PR15662: Optimized debug info produces out of order function parameters
When a function is inlined we lazily construct the variables
representing the function's parameters. After that, we add any remaining
unused parameters.

If the function doesn't use all the parameters, or uses them out of
order, then the DWARF would produce them in that order, producing a
parameter order that doesn't match the source.

This fix causes us to always keep the arg variables at the start of the
variable list & in the original order from the source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183297 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 05:39:59 +00:00
Tom Stellard
ad7ecc65b1 R600: Make sure to schedule AR register uses and defs in the same clause
Reviewed-by: vljn at ovi.com

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 03:43:06 +00:00
Rafael Espindola
23a22cdedd Don't print default values for NumberOfAuxSymbols and AuxiliaryData.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 03:20:13 +00:00
Rafael Espindola
6afb65c2b7 Revert "R600: Add a pass that merge Vector Register"
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:48:30 +00:00
Rafael Espindola
6c1202c459 Handle relocations that don't point to symbols.
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:33:53 +00:00
Vincent Lejeune
bbbdba891b R600: Add a pass that merge Vector Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d R600: Const/Neg/Abs can be folded to dot4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:15 +00:00
Evan Cheng
00ed010d9e Cortex-R5 can issue Thumb2 integer division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:52:09 +00:00
David Majnemer
5a57dbef33 IndVarSimplify: check if loop invariant expansion can trap
IndVarSimplify is willing to move divide instructions outside of their
loop bodies if they are invariant of the loop.  However, it may not be
safe to expand them if we do not know if they can trap.

Instead, check to see if it is not safe to expand the instruction and
skip the expansion.

This fixes PR16041.

Testcase by Rafael Ávila de Espíndola.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183239 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 17:51:58 +00:00
David Majnemer
35e7751af4 ARM: Fix crash in ARM backend inside of ARMConstantIslandPass
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 17:46:15 +00:00
Vincent Lejeune
98017a015b R600: Swizzle texture/export instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 15:04:53 +00:00
Vincent Lejeune
9328438329 R600: Add a test for r183108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 15:03:35 +00:00
Rafael Espindola
babae05237 Second part of pr16069
The problem this time seems to be a thinko. We were assuming that in the CFG

A
| \
|  B
| /
C

speculating the basic block B would cause only the phi value for the B->C edge
to be speculated. That is not true, the phi's are semantically in the edges, so
if the A->B->C path is taken, any code needed for A->C is not executed and we
have to consider it too when deciding to speculate B.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 14:11:59 +00:00
Alexey Samsonov
888ca964a4 [llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume that symbols with zero size are in fact large enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 07:57:38 +00:00
David Majnemer
3931bdb788 SimplifyCFG: Do not transform PHI to select if doing so would be unsafe
PR16069 is an interesting case where an incoming value to a PHI is a
trap value while also being a 'ConstantExpr'.

We do not consider this case when performing the 'HoistThenElseCodeToIf'
optimization.

Instead, make our modifications more conservative if we detect that we
cannot transform the PHI to a select.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 20:43:12 +00:00
Rafael Espindola
d1100b3325 Enable mcjit tests on ppc64 when building with cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 19:17:21 +00:00
Tom Stellard
e5fcc0dee4 R600/SI: Add support for work item and work group intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:18 +00:00
Tom Stellard
e7397ee81a R600/SI: Add a calling convention for compute shaders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:11 +00:00
Tom Stellard
e86f9d70ca R600/SI: Custom lower i64 sign_extend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:03 +00:00
Tom Stellard
132183510f R600/SI: Add support for global loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:39:43 +00:00
Vincent Lejeune
96fe0be43b R600: use capital letter for PV channel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 15:44:35 +00:00
Alexey Samsonov
625b109916 Correct handling invalid filename in llvm-symbolizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 14:12:39 +00:00
Venkatraman Govindaraju
e7cbb792c9 Sparc: Add support for indirect branch and blockaddress in Sparc backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 05:58:33 +00:00
Rui Ueyama
891c0cd3c1 [Object/COFF] Fix Windows .lib name handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 00:27:03 +00:00
Venkatraman Govindaraju
85cc972a06 Sparc: When storing 0, use %g0 directly in the store instruction instead of
using two instructions (sethi and store).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 00:21:54 +00:00
Venkatraman Govindaraju
65ca7aa57d Sparc: Combine add/or/sethi instruction with restore if possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-02 21:48:17 +00:00
Venkatraman Govindaraju
dd48226b15 Sparc: Perform leaf procedure optimization by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-02 02:24:27 +00:00
Nick Lewycky
e4546cb71e When determining the new index for an insertelement, we may not assume that an
index greater than the size of the vector is invalid. The shuffle may be
shrinking the size of the vector. Fixes a crash!

Also drop the maximum recursion depth of the safety check for this
optimization to five.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183080 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 20:51:31 +00:00
Venkatraman Govindaraju
a0b34d6c4a Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183079 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 20:42:48 +00:00
Tim Northover
95a565a063 Disable new legacy JIT test on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 10:24:11 +00:00
Tim Northover
3ba14fab1b Revert r183069: "TMP: LEA64_32r fixing"
Very sorry, it was committed from the wrong branch by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 10:23:46 +00:00
Tim Northover
4d3ace4da0 TMP: LEA64_32r fixing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 10:21:54 +00:00
Tim Northover
85c622d6b6 X86: change MOV64ri64i32 into MOV32ri64
The MOV64ri64i32 instruction required hacky MCInst lowering because it
was allocated as setting a GR64, but the eventual instruction ("movl")
only set a GR32. This converts it into a so-called "MOV32ri64" which
still accepts a (appropriate) 64-bit immediate but defines a GR32.
This is then converted to the full GR64 by a SUBREG_TO_REG operation,
thus keeping everyone happy.

This fixes a typo in the opcode field of the original patch, which
should make the legact JIT work again (& adds test for that problem).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 09:55:14 +00:00
Venkatraman Govindaraju
72ad17c48c [Sparc] Generate correct code for leaf functions with stack objects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01 04:51:18 +00:00
Andrew Trick
cd8e3c4dcf Prevent loop-unroll from making assumptions about undefined behavior.
Fixes rdar:14036816, PR16130.

There is an opportunity to compute precise trip counts for 'or'
expressions and multi-exit loops.
rdar:14038809: Optimize trip count computation for multi-exit loops.

To do this we need to record the fact that ExitLimit assumes NSW. When
it does not we can safely assume that the loop trip count is the
minimum ExitLimt across all subexpressions and loop exits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-31 23:34:46 +00:00