mirror of
https://github.com/c64scene-ar/llvm-6502.git
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4a888086a4
Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240839 91177308-0d34-0410-b5e6-96231b3b80d8
298 lines
13 KiB
C++
298 lines
13 KiB
C++
//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides AMDGPU specific target streamer methods.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetStreamer.h"
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#include "SIDefines.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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AMDGPUTargetStreamer::AMDGPUTargetStreamer(MCStreamer &S)
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: MCTargetStreamer(S) { }
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//===----------------------------------------------------------------------===//
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// AMDGPUTargetAsmStreamer
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//===----------------------------------------------------------------------===//
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AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS)
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: AMDGPUTargetStreamer(S), OS(OS) { }
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void
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AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(uint32_t Major,
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uint32_t Minor) {
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OS << "\t.hsa_code_object_version " <<
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Twine(Major) << "," << Twine(Minor) << '\n';
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}
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void
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AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
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uint32_t Minor,
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uint32_t Stepping,
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StringRef VendorName,
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StringRef ArchName) {
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OS << "\t.hsa_code_object_isa " <<
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Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) <<
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",\"" << VendorName << "\",\"" << ArchName << "\"\n";
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}
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void
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AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
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uint64_t ComputePgmRsrc2 = (Header.compute_pgm_resource_registers >> 32);
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bool EnableSGPRPrivateSegmentBuffer = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
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bool EnableSGPRDispatchPtr = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
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bool EnableSGPRQueuePtr = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
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bool EnableSGPRKernargSegmentPtr = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
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bool EnableSGPRDispatchID = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
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bool EnableSGPRFlatScratchInit = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
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bool EnableSGPRPrivateSegmentSize = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
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bool EnableSGPRGridWorkgroupCountX = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X);
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bool EnableSGPRGridWorkgroupCountY = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y);
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bool EnableSGPRGridWorkgroupCountZ = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z);
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bool EnableOrderedAppendGDS = (Header.code_properties &
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AMD_CODE_PROPERTY_ENABLE_ORDERED_APPEND_GDS);
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uint32_t PrivateElementSize = (Header.code_properties &
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AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE) >>
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AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE_SHIFT;
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bool IsPtr64 = (Header.code_properties & AMD_CODE_PROPERTY_IS_PTR64);
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bool IsDynamicCallstack = (Header.code_properties &
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AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK);
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bool IsDebugEnabled = (Header.code_properties &
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AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED);
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bool IsXNackEnabled = (Header.code_properties &
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AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED);
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OS << "\t.amd_kernel_code_t\n" <<
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"\t\tkernel_code_version_major = " <<
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Header.amd_kernel_code_version_major << '\n' <<
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"\t\tkernel_code_version_minor = " <<
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Header.amd_kernel_code_version_minor << '\n' <<
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"\t\tmachine_kind = " <<
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Header.amd_machine_kind << '\n' <<
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"\t\tmachine_version_major = " <<
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Header.amd_machine_version_major << '\n' <<
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"\t\tmachine_version_minor = " <<
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Header.amd_machine_version_minor << '\n' <<
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"\t\tmachine_version_stepping = " <<
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Header.amd_machine_version_stepping << '\n' <<
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"\t\tkernel_code_entry_byte_offset = " <<
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Header.kernel_code_entry_byte_offset << '\n' <<
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"\t\tkernel_code_prefetch_byte_size = " <<
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Header.kernel_code_prefetch_byte_size << '\n' <<
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"\t\tmax_scratch_backing_memory_byte_size = " <<
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Header.max_scratch_backing_memory_byte_size << '\n' <<
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"\t\tcompute_pgm_rsrc1_vgprs = " <<
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G_00B848_VGPRS(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc1_sgprs = " <<
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G_00B848_SGPRS(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc1_priority = " <<
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G_00B848_PRIORITY(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc1_float_mode = " <<
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G_00B848_FLOAT_MODE(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc1_priv = " <<
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G_00B848_PRIV(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc1_dx10_clamp = " <<
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G_00B848_DX10_CLAMP(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc1_debug_mode = " <<
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G_00B848_DEBUG_MODE(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc1_ieee_mode = " <<
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G_00B848_IEEE_MODE(Header.compute_pgm_resource_registers) << '\n' <<
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"\t\tcompute_pgm_rsrc2_scratch_en = " <<
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G_00B84C_SCRATCH_EN(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_user_sgpr = " <<
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G_00B84C_USER_SGPR(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_tgid_x_en = " <<
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G_00B84C_TGID_X_EN(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_tgid_y_en = " <<
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G_00B84C_TGID_Y_EN(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_tgid_z_en = " <<
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G_00B84C_TGID_Z_EN(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_tg_size_en = " <<
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G_00B84C_TG_SIZE_EN(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_tidig_comp_cnt = " <<
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G_00B84C_TIDIG_COMP_CNT(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_excp_en_msb = " <<
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G_00B84C_EXCP_EN_MSB(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_lds_size = " <<
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G_00B84C_LDS_SIZE(ComputePgmRsrc2) << '\n' <<
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"\t\tcompute_pgm_rsrc2_excp_en = " <<
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G_00B84C_EXCP_EN(ComputePgmRsrc2) << '\n' <<
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"\t\tenable_sgpr_private_segment_buffer = " <<
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EnableSGPRPrivateSegmentBuffer << '\n' <<
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"\t\tenable_sgpr_dispatch_ptr = " <<
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EnableSGPRDispatchPtr << '\n' <<
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"\t\tenable_sgpr_queue_ptr = " <<
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EnableSGPRQueuePtr << '\n' <<
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"\t\tenable_sgpr_kernarg_segment_ptr = " <<
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EnableSGPRKernargSegmentPtr << '\n' <<
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"\t\tenable_sgpr_dispatch_id = " <<
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EnableSGPRDispatchID << '\n' <<
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"\t\tenable_sgpr_flat_scratch_init = " <<
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EnableSGPRFlatScratchInit << '\n' <<
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"\t\tenable_sgpr_private_segment_size = " <<
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EnableSGPRPrivateSegmentSize << '\n' <<
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"\t\tenable_sgpr_grid_workgroup_count_x = " <<
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EnableSGPRGridWorkgroupCountX << '\n' <<
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"\t\tenable_sgpr_grid_workgroup_count_y = " <<
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EnableSGPRGridWorkgroupCountY << '\n' <<
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"\t\tenable_sgpr_grid_workgroup_count_z = " <<
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EnableSGPRGridWorkgroupCountZ << '\n' <<
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"\t\tenable_ordered_append_gds = " <<
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EnableOrderedAppendGDS << '\n' <<
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"\t\tprivate_element_size = " <<
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PrivateElementSize << '\n' <<
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"\t\tis_ptr64 = " <<
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IsPtr64 << '\n' <<
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"\t\tis_dynamic_callstack = " <<
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IsDynamicCallstack << '\n' <<
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"\t\tis_debug_enabled = " <<
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IsDebugEnabled << '\n' <<
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"\t\tis_xnack_enabled = " <<
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IsXNackEnabled << '\n' <<
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"\t\tworkitem_private_segment_byte_size = " <<
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Header.workitem_private_segment_byte_size << '\n' <<
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"\t\tworkgroup_group_segment_byte_size = " <<
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Header.workgroup_group_segment_byte_size << '\n' <<
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"\t\tgds_segment_byte_size = " <<
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Header.gds_segment_byte_size << '\n' <<
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"\t\tkernarg_segment_byte_size = " <<
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Header.kernarg_segment_byte_size << '\n' <<
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"\t\tworkgroup_fbarrier_count = " <<
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Header.workgroup_fbarrier_count << '\n' <<
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"\t\twavefront_sgpr_count = " <<
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Header.wavefront_sgpr_count << '\n' <<
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"\t\tworkitem_vgpr_count = " <<
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Header.workitem_vgpr_count << '\n' <<
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"\t\treserved_vgpr_first = " <<
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Header.reserved_vgpr_first << '\n' <<
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"\t\treserved_vgpr_count = " <<
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Header.reserved_vgpr_count << '\n' <<
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"\t\treserved_sgpr_first = " <<
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Header.reserved_sgpr_first << '\n' <<
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"\t\treserved_sgpr_count = " <<
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Header.reserved_sgpr_count << '\n' <<
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"\t\tdebug_wavefront_private_segment_offset_sgpr = " <<
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Header.debug_wavefront_private_segment_offset_sgpr << '\n' <<
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"\t\tdebug_private_segment_buffer_sgpr = " <<
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Header.debug_private_segment_buffer_sgpr << '\n' <<
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"\t\tkernarg_segment_alignment = " <<
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(uint32_t)Header.kernarg_segment_alignment << '\n' <<
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"\t\tgroup_segment_alignment = " <<
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(uint32_t)Header.group_segment_alignment << '\n' <<
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"\t\tprivate_segment_alignment = " <<
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(uint32_t)Header.private_segment_alignment << '\n' <<
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"\t\twavefront_size = " <<
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(uint32_t)Header.wavefront_size << '\n' <<
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"\t\tcall_convention = " <<
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Header.call_convention << '\n' <<
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"\t\truntime_loader_kernel_symbol = " <<
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Header.runtime_loader_kernel_symbol << '\n' <<
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// TODO: control_directives
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"\t.end_amd_kernel_code_t\n";
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}
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//===----------------------------------------------------------------------===//
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// AMDGPUTargetELFStreamer
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//===----------------------------------------------------------------------===//
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AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S)
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: AMDGPUTargetStreamer(S), Streamer(S) { }
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MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
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return static_cast<MCELFStreamer &>(Streamer);
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}
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void
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AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(uint32_t Major,
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uint32_t Minor) {
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MCStreamer &OS = getStreamer();
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MCSectionELF *Note = OS.getContext().getELFSection(".note", ELF::SHT_NOTE, 0);
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unsigned NameSZ = 4;
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OS.PushSection();
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OS.SwitchSection(Note);
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OS.EmitIntValue(NameSZ, 4); // namesz
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OS.EmitIntValue(8, 4); // descz
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OS.EmitIntValue(NT_AMDGPU_HSA_CODE_OBJECT_VERSION, 4); // type
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OS.EmitBytes(StringRef("AMD", NameSZ)); // name
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OS.EmitIntValue(Major, 4); // desc
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OS.EmitIntValue(Minor, 4);
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OS.EmitValueToAlignment(4);
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OS.PopSection();
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}
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void
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AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
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uint32_t Minor,
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uint32_t Stepping,
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StringRef VendorName,
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StringRef ArchName) {
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MCStreamer &OS = getStreamer();
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MCSectionELF *Note = OS.getContext().getELFSection(".note", ELF::SHT_NOTE, 0);
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unsigned NameSZ = 4;
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uint16_t VendorNameSize = VendorName.size() + 1;
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uint16_t ArchNameSize = ArchName.size() + 1;
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unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
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sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
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VendorNameSize + ArchNameSize;
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OS.PushSection();
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OS.SwitchSection(Note);
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OS.EmitIntValue(NameSZ, 4); // namesz
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OS.EmitIntValue(DescSZ, 4); // descsz
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OS.EmitIntValue(NT_AMDGPU_HSA_ISA, 4); // type
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OS.EmitBytes(StringRef("AMD", 4)); // name
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OS.EmitIntValue(VendorNameSize, 2); // desc
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OS.EmitIntValue(ArchNameSize, 2);
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OS.EmitIntValue(Major, 4);
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OS.EmitIntValue(Minor, 4);
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OS.EmitIntValue(Stepping, 4);
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OS.EmitBytes(VendorName);
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OS.EmitIntValue(0, 1); // NULL terminate VendorName
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OS.EmitBytes(ArchName);
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OS.EmitIntValue(0, 1); // NULL terminte ArchName
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OS.EmitValueToAlignment(4);
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OS.PopSection();
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}
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void
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AMDGPUTargetELFStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
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MCStreamer &OS = getStreamer();
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OS.PushSection();
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OS.SwitchSection(OS.getContext().getObjectFileInfo()->getTextSection());
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OS.EmitBytes(StringRef((const char*)&Header, sizeof(Header)));
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OS.PopSection();
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}
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