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AsmParser
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[llvm-mc] Pushing plumbing through for --fatal-warnings flag.
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2015-07-27 21:56:53 +00:00 |
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InstPrinter
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MCTargetDesc
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AMDGPU: Fix unreachable when emitting binary debug info
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2015-07-30 17:03:08 +00:00 |
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TargetInfo
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Utils
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AMDGPU.h
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AMDGPU.td
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AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets
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2015-07-16 19:40:07 +00:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Minor cleanups to always inline pass
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2015-07-13 19:08:36 +00:00 |
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AMDGPUAsmPrinter.cpp
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
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Fix broken ArrayRef conversion from r243497.
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2015-07-28 23:34:27 +00:00 |
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AMDGPUInstrInfo.h
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MIR Serialization: Serialize the target index machine operands.
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2015-07-28 23:02:45 +00:00 |
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AMDGPUInstrInfo.td
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AMDGPUInstructions.td
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AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
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AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops
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2015-07-20 14:28:41 +00:00 |
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AMDGPUISelLowering.cpp
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AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
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2015-07-14 18:20:33 +00:00 |
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AMDGPUISelLowering.h
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AMDGPU: Fix return type of getImplicitParameterOffset.
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2015-07-28 18:09:55 +00:00 |
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AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPUPromoteAlloca.cpp
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De-constify pointers to Type since they can't be modified. NFC
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2015-08-01 22:20:21 +00:00 |
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPU: Set SubRegIndex size and offset
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2015-07-30 17:03:11 +00:00 |
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AMDGPUSubtarget.cpp
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AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets
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2015-07-16 19:40:07 +00:00 |
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AMDGPUSubtarget.h
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AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets
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2015-07-16 19:40:07 +00:00 |
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AMDGPUTargetMachine.cpp
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AMDGPU/SI: Fix read2 merging into a super register.
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2015-07-14 17:57:36 +00:00 |
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AMDGPUTargetMachine.h
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AMDGPUTargetTransformInfo.cpp
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AMDGPUTargetTransformInfo.h
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AMDILCFGStructurizer.cpp
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AMDGPU/R600: Remove unused variable
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2015-07-16 16:13:34 +00:00 |
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AMDKernelCodeT.h
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CaymanInstructions.td
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CIInstructions.td
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CMakeLists.txt
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EvergreenInstructions.td
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LLVMBuild.txt
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Makefile
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Processors.td
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrFormats.td
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R600InstrInfo.cpp
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R600InstrInfo.h
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R600Instructions.td
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R600Intrinsics.td
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R600ISelLowering.cpp
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Add missing break in switch case in R600ISelLowering
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2015-07-16 06:23:12 +00:00 |
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R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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[PM/AA] Remove all of the dead AliasAnalysis pointers being threaded
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2015-07-22 09:52:54 +00:00 |
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SIDefines.h
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SIFixControlFlowLiveIntervals.cpp
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SIFixSGPRCopies.cpp
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SIFixSGPRLiveRanges.cpp
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SIFoldOperands.cpp
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SIInsertWaits.cpp
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SIInstrFormats.td
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SIInstrInfo.cpp
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AMDGPU/SI: Add implicit register operands in the correct order.
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2015-07-31 23:30:09 +00:00 |
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SIInstrInfo.h
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AMDGPU/SI: Add implicit register operands in the correct order.
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2015-07-31 23:30:09 +00:00 |
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SIInstrInfo.td
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SIInstructions.td
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AMDGPU/SI: Remove unused pattern for f32 constant loads
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2015-07-31 01:02:32 +00:00 |
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SIIntrinsics.td
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SIISelLowering.cpp
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De-constify pointers to Type since they can't be modified. NFC
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2015-08-01 22:20:21 +00:00 |
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SIISelLowering.h
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AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops
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2015-07-20 14:28:41 +00:00 |
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SILoadStoreOptimizer.cpp
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AMDGPU/SI: Fix read2 merging into a super register.
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2015-07-14 17:57:36 +00:00 |
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SILowerControlFlow.cpp
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SILowerI1Copies.cpp
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SIMachineFunctionInfo.cpp
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MachineRegisterInfo: Remove UsedPhysReg infrastructure
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2015-07-14 17:52:07 +00:00 |
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SIMachineFunctionInfo.h
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SIPrepareScratchRegs.cpp
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MachineRegisterInfo: Remove UsedPhysReg infrastructure
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2015-07-14 17:52:07 +00:00 |
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SIRegisterInfo.cpp
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MachineRegisterInfo: Remove UsedPhysReg infrastructure
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2015-07-14 17:52:07 +00:00 |
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SIRegisterInfo.h
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SIRegisterInfo.td
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AMDGPU/SI: Set DwarfRegNum
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2015-07-31 01:12:10 +00:00 |
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SISchedule.td
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SIShrinkInstructions.cpp
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AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
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2015-07-14 14:15:03 +00:00 |
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SITypeRewriter.cpp
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VIInstrFormats.td
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VIInstructions.td
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AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops
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2015-07-20 14:28:41 +00:00 |
