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https://github.com/c64scene-ar/llvm-6502.git
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Hans Wennborg
d0702afadf
------------------------------------------------------------------------ r243638 | vkalintiris | 2015-07-30 05:39:33 -0700 (Thu, 30 Jul 2015) | 12 lines [mips][FastISel] Remove hidden mips-fast-isel option. Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r243640 | vkalintiris | 2015-07-30 06:13:09 -0700 (Thu, 30 Jul 2015) | 5 lines [mips] Fix out-of-date debug information in test file. Update the debug info in the check-lines because the change in r243638 introduced a constant initialization before the prologue's end as part of a register spill. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@243650 91177308-0d34-0410-b5e6-96231b3b80d8
17 lines
539 B
LLVM
17 lines
539 B
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic
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; The test is just to make sure it is able to allocate
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; registers for this example. There was an issue with allocating AC0
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; after a mul instruction.
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declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
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define i32 @foo(i32 %a, i32 %b) {
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entry:
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%0 = mul i32 %a, %b
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%1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b)
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%2 = extractvalue { i32, i1 } %1, 0
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ret i32 %2
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}
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