mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-20 16:17:38 +00:00
Hans Wennborg
d0702afadf
------------------------------------------------------------------------ r243638 | vkalintiris | 2015-07-30 05:39:33 -0700 (Thu, 30 Jul 2015) | 12 lines [mips][FastISel] Remove hidden mips-fast-isel option. Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r243640 | vkalintiris | 2015-07-30 06:13:09 -0700 (Thu, 30 Jul 2015) | 5 lines [mips] Fix out-of-date debug information in test file. Update the debug info in the check-lines because the change in r243638 introduced a constant initialization before the prologue's end as part of a register spill. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@243650 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.1 KiB
LLVM
69 lines
2.1 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@ijk = external global i32
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; Function Attrs: nounwind
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define void @si2_1() #0 {
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entry:
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store i32 32767, i32* @ijk, align 4
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; CHECK: .ent si2_1
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; CHECK: addiu $[[REG1:[0-9]+]], $zero, 32767
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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; Function Attrs: nounwind
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define void @si2_2() #0 {
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entry:
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store i32 -32768, i32* @ijk, align 4
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; CHECK: .ent si2_2
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; CHECK: lui $[[REG1:[0-9]+]], 65535
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; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768
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; CHECK: lw $[[REG3:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG2]], 0($[[REG3]])
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ret void
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}
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; Function Attrs: nounwind
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define void @ui2_1() #0 {
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entry:
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store i32 65535, i32* @ijk, align 4
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; CHECK: .ent ui2_1
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; CHECK: ori $[[REG1:[0-9]+]], $zero, 65535
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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; Function Attrs: nounwind
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define void @ui4_1() #0 {
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entry:
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store i32 983040, i32* @ijk, align 4
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; CHECK: .ent ui4_1
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; CHECK: lui $[[REG1:[0-9]+]], 15
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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; Function Attrs: nounwind
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define void @ui4_2() #0 {
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entry:
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store i32 719566, i32* @ijk, align 4
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; CHECK: .ent ui4_2
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; CHECK: lui $[[REG1:[0-9]+]], 10
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; CHECK: ori $[[REG1]], $[[REG1]], 64206
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; CHECK: lw $[[REG2:[0-9]+]], %got(ijk)(${{[0-9]+}})
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; CHECK: sw $[[REG1]], 0($[[REG2]])
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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