mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-04 06:09:05 +00:00
d2e1e42c1a
When FixedLenDecoder matches an input bitpattern of form [01]+ with an instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are mixed/variable bits) it passes the input bitpattern to a specific instruction decoder method which then makes a final decision whether the bitpattern is a valid instruction or not. This means the decoder must handle all possible values of the variable bits which sometimes leads to opcode rewrites in the decoder method when the instructions are not fully orthogonal. The patch provides a way for the decoder method to say that when it returns Fail it does not necessarily mean the bitpattern is invalid, but rather that the bitpattern is definitely not an instruction that is recognized by the decoder method. The decoder can then try to match the input bitpattern with other possible instruction bitpatterns. For example, this allows to solve a situation on AArch64 where the `MSR (immediate)` instruction has form: 1101 0101 0000 0??? 0100 ???? ???1 1111 but not all values of the ? bits are allowed. The rejected values should be handled by the `extended MSR (register)` instruction: 1101 0101 000? ???? ???? ???? ???? ???? The decoder will first try to decode an input bitpattern that matches both bitpatterns as `MSR (immediate)` but currently this puts the decoder method of `MSR (immediate)` into a situation when it must be able to decode all possible values of the ? bits, i.e. it would need to rewrite the instruction to `MSR (register)` when it is not `MSR (immediate)`. The patch allows to specify that the decoder method cannot determine if the instruction is valid for all variable values. The decoder method can simply return Fail when it knows it is definitely not `MSR (immediate)`. The decoder will then backtrack the decoding and find that it can match the input bitpattern with the more generic `MSR (register)` bitpattern too. Differential Revision: http://reviews.llvm.org/D7174 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242274 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
|---|---|---|
| .. | ||
| 2003-08-03-PassCode.td | ||
| 2006-09-18-LargeInt.td | ||
| 2010-03-24-PrematureDefaults.td | ||
| AnonDefinitionOnDemand.td | ||
| AsmPredicateCondsEmission.td | ||
| BitOffsetDecoder.td | ||
| BitsInit.td | ||
| BitsInitOverflow.td | ||
| cast.td | ||
| ClassInstanceValue.td | ||
| CStyleComment.td | ||
| Dag.td | ||
| defmclass.td | ||
| DefmInherit.td | ||
| DefmInsideMultiClass.td | ||
| eq.td | ||
| eqbit.td | ||
| FieldAccess.td | ||
| foreach.td | ||
| ForeachList.td | ||
| ForeachLoop.td | ||
| ForwardRef.td | ||
| GeneralList.td | ||
| if-empty-list-arg.td | ||
| if.td | ||
| ifbit.td | ||
| Include.inc | ||
| Include.td | ||
| IntBitInit.td | ||
| intrinsic-long-name.td | ||
| intrinsic-order.td | ||
| intrinsic-varargs.td | ||
| LazyChange.td | ||
| LetInsideMultiClasses.td | ||
| lisp.td | ||
| list-element-bitref.td | ||
| ListArgs.td | ||
| ListArgsSimple.td | ||
| listconcat.td | ||
| ListConversion.td | ||
| ListManip.td | ||
| ListOfList.td | ||
| ListSlices.td | ||
| lit.local.cfg | ||
| LoLoL.td | ||
| math.td | ||
| MultiClass.td | ||
| MultiClassDefName.td | ||
| MultiClassInherit.td | ||
| MultiPat.td | ||
| nested-comment.td | ||
| NestedForeach.td | ||
| Paste.td | ||
| pr8330.td | ||
| SetTheory.td | ||
| SiblingForeach.td | ||
| Slice.td | ||
| strconcat.td | ||
| String.td | ||
| subst2.td | ||
| subst.td | ||
| SuperSubclassSameName.td | ||
| TargetInstrInfo.td | ||
| TargetInstrSpec.td | ||
| TemplateArgRename.td | ||
| Tree.td | ||
| TreeNames.td | ||
| trydecode-emission2.td | ||
| trydecode-emission3.td | ||
| trydecode-emission.td | ||
| TwoLevelName.td | ||
| UnsetBitInit.td | ||
| UnterminatedComment.td | ||
| usevalname.td | ||
| ValidIdentifiers.td | ||